Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Create procedural generation for Verilog | Yann Herklotz Grave | 2019-03-04 | 1 | -12/+3 |
* | Fix all the warnings and fix building | Yann Herklotz Grave | 2019-03-03 | 1 | -10/+15 |
* | Add transformers and procedural generation | Yann Herklotz Grave | 2019-03-03 | 1 | -11/+84 |
* | Reformat using brittany | Yann Herklotz Grave | 2019-02-25 | 1 | -1/+6 |
* | Indent by 4 | Yann Herklotz Grave | 2019-02-17 | 1 | -24/+24 |
* | Brittany formatting | Yann Herklotz Grave | 2019-02-17 | 1 | -16/+14 |
* | Change Port type, adding signed info | Yann Herklotz Grave | 2019-02-16 | 1 | -8/+9 |
* | Small fixes to module generation | Yann Herklotz | 2019-02-03 | 1 | -4/+7 |
* | Add mutation to declare other wires | Yann Herklotz | 2019-02-02 | 1 | -7/+28 |
* | Remove last warning | Yann Herklotz | 2019-02-01 | 1 | -1/+4 |
* | Small warning fix | Yann Herklotz | 2019-02-01 | 1 | -1/+1 |
* | Fix all the compile and test errors | Yann Herklotz | 2019-02-01 | 1 | -8/+19 |
* | Fix imports | Yann Herklotz | 2019-02-01 | 1 | -2/+2 |
* | Structure changes | Yann Herklotz | 2019-02-01 | 1 | -0/+35 |