| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename to Verilog | Yann Herklotz | 2019-04-02 | 1 | -11/+10 |
| * | Fix hlint hints | Yann Herklotz | 2019-04-02 | 1 | -6/+7 |
| * | Run through brittany | Yann Herklotz | 2019-04-01 | 3 | -134/+158 |
| * | Fix warnings in code | Yann Herklotz | 2019-03-31 | 1 | -24/+7 |
| * | Fix some of the tests | Yann Herklotz | 2019-03-31 | 1 | -1/+2 |
| * | Rewrite the parser with real lexer | Yann Herklotz | 2019-03-31 | 4 | -0/+941 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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