verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add transformers and procedural generation	Yann Herklotz Grave	2019-03-03	1	-12/+12
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*	Add .gitAttributes	Yann Herklotz Grave	2019-03-03	1	-1/+1
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*	Add applicative instance and Expr reduction	Yann Herklotz Grave	2019-03-02	1	-20/+48
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*	Some formatting	Yann Herklotz Grave	2019-03-01	1	-4/+4
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*	Add better reduction with custom type	Yann Herklotz Grave	2019-03-01	1	-48/+73
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*	[Fix #35] Add reducer that tries and reduce Verilog given a run	Yann Herklotz Grave	2019-03-01	1	-24/+94
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*	Add Ord to AST and fix reduction function	Yann Herklotz Grave	2019-02-26	1	-2/+4
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*	Add recursive reduce call	Yann Herklotz Grave	2019-02-25	1	-6/+31
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*	Reformat using brittany	Yann Herklotz Grave	2019-02-25	1	-1/+2
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*	Brittany formatting	Yann Herklotz Grave	2019-02-17	1	-5/+2
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*	Fix reduce build	Yann Herklotz Grave	2019-02-11	1	-2/+1
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*	Fix reducer	Yann Herklotz Grave	2019-02-11	1	-1/+1
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*	Add Reduce which will contain the test reduction	Yann Herklotz	2019-02-08	1	-0/+29