| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -16/+12 |
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| * | Format files | Yann Herklotz | 2019-06-29 | 1 | -11/+15 |
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| * | Format all files | Yann Herklotz | 2019-06-05 | 1 | -29/+27 |
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| * | Add check for quicker reduction | Yann Herklotz | 2019-06-02 | 1 | -17/+19 |
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| * | Fix reduction for statements | Yann Herklotz | 2019-05-25 | 1 | -12/+14 |
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| * | Add synthesis fails to fuzzer | Yann Herklotz | 2019-05-25 | 1 | -0/+1 |
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| * | Add reducesynthesis function | Yann Herklotz | 2019-05-25 | 1 | -0/+13 |
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| * | No expression reduction | Yann Herklotz | 2019-05-24 | 1 | -1/+1 |
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| * | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 1 | -13/+22 |
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| * | Reduction throws away path if it finds a passing one | Yann Herklotz | 2019-05-24 | 1 | -19/+16 |
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| * | Change simple graph check to acyclic check | Yann Herklotz | 2019-05-19 | 1 | -6/+8 |
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| * | Add ability to clean up verilog file | Yann Herklotz | 2019-05-15 | 1 | -3/+115 |
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| * | Add cleaning on all modules | Yann Herklotz | 2019-05-14 | 1 | -17/+24 |
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| * | Add reduction for multiple modules | Yann Herklotz | 2019-05-14 | 1 | -29/+72 |
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| * | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -107/+108 |
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| * | Add optimisation to check if at bottom | Yann Herklotz | 2019-05-13 | 1 | -17/+40 |
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| * | Add reduction to fuzz run | Yann Herklotz | 2019-05-13 | 1 | -1/+1 |
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| * | Inverse case statement | Yann Herklotz | 2019-05-13 | 1 | -3/+3 |
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| * | Add reducer function for two arbitrary Synthesiser | Yann Herklotz | 2019-05-13 | 1 | -4/+13 |
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| * | Add NonEmpty to tests | Yann Herklotz | 2019-05-13 | 1 | -2/+1 |
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| * | Add reduction for the commandline | Yann Herklotz | 2019-05-13 | 1 | -29/+84 |
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| * | Add working statement reduction | Yann Herklotz | 2019-05-12 | 1 | -30/+60 |
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| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 1 | -5/+10 |
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| * | Fix warnings for CI | Yann Herklotz | 2019-05-11 | 1 | -3/+3 |
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| * | Add new reduction techniques | Yann Herklotz | 2019-05-11 | 1 | -121/+93 |
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| * | Fix but remove the doctests for now | Yann Herklotz | 2019-05-10 | 1 | -25/+25 |
| | | | | | | They were not working well with the current printing method. I have to find a way to remove the spaces from the output. | ||||
| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 1 | -11/+156 |
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| * | Add combinational and sequential logic support | Yann Herklotz | 2019-05-09 | 1 | -3/+15 |
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| * | Support multiple reg assigns in if statements | Yann Herklotz | 2019-05-06 | 1 | -6/+6 |
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| * | Format with brittany | Yann Herklotz | 2019-05-05 | 1 | -3/+3 |
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| * | Add more reduction to tests | Yann Herklotz | 2019-04-29 | 1 | -2/+10 |
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| * | Move Reduce file | Yann Herklotz | 2019-04-17 | 1 | -0/+164 |
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| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -176/+0 |
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| * | Change license name | Yann Herklotz | 2019-03-30 | 1 | -1/+1 |
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| * | Add transformers and procedural generation | Yann Herklotz Grave | 2019-03-03 | 1 | -12/+12 |
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| * | Add .gitAttributes | Yann Herklotz Grave | 2019-03-03 | 1 | -1/+1 |
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| * | Add applicative instance and Expr reduction | Yann Herklotz Grave | 2019-03-02 | 1 | -20/+48 |
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| * | Some formatting | Yann Herklotz Grave | 2019-03-01 | 1 | -4/+4 |
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| * | Add better reduction with custom type | Yann Herklotz Grave | 2019-03-01 | 1 | -48/+73 |
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| * | [Fix #35] Add reducer that tries and reduce Verilog given a run | Yann Herklotz Grave | 2019-03-01 | 1 | -24/+94 |
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| * | Add Ord to AST and fix reduction function | Yann Herklotz Grave | 2019-02-26 | 1 | -2/+4 |
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| * | Add recursive reduce call | Yann Herklotz Grave | 2019-02-25 | 1 | -6/+31 |
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| * | Reformat using brittany | Yann Herklotz Grave | 2019-02-25 | 1 | -1/+2 |
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| * | Brittany formatting | Yann Herklotz Grave | 2019-02-17 | 1 | -5/+2 |
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| * | Fix reduce build | Yann Herklotz Grave | 2019-02-11 | 1 | -2/+1 |
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| * | Fix reducer | Yann Herklotz Grave | 2019-02-11 | 1 | -1/+1 |
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| * | Add Reduce which will contain the test reduction | Yann Herklotz | 2019-02-08 | 1 | -0/+29 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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