| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update simulator with Result type | Yann Herklotz | 2019-04-17 | 1 | -15/+57 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 1 | -20/+0 |
| * | Rename Synthesisor -> Synthesiser | Yann Herklotz | 2019-04-15 | 1 | -4/+4 |
| * | Print out local time | Yann Herklotz | 2019-04-14 | 1 | -2/+5 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -1/+1 |
| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -2/+2 |
| * | Fix to the logger | Yann Herklotz | 2019-04-03 | 1 | -0/+10 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+112 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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