verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renaming to VeriSmith	Yann Herklotz	2019-09-04	1	-215/+0
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*	Change name from VeriFuzz to VeriSmith	Yann Herklotz	2019-08-29	1	-8/+8
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*	Add new maintainer email	Yann Herklotz	2019-07-23	1	-20/+14
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*	Format files	Yann Herklotz	2019-06-29	1	-13/+19
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*	Add timeout error to synthesisers	Yann Herklotz	2019-05-25	1	-7/+14
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*	Add renameSource	Yann Herklotz	2019-05-14	1	-0/+5
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*	Add more reporting to equivalence check	Yann Herklotz	2019-05-13	1	-0/+2
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*	Add ResultT to Sh conversion	Yann Herklotz	2019-05-13	1	-0/+10
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*	Use abc for verification	Yann Herklotz	2019-05-07	1	-4/+2
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*	Create better command line output	Yann Herklotz	2019-05-07	1	-1/+8
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*	Rename some functions to use nicer names	Yann Herklotz	2019-05-07	1	-12/+18
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*	Add support for multiple modules	Yann Herklotz	2019-05-07	1	-2/+34
\| \| \| \| \| \| \|	Had to manually change module names, as Yosys does not change the module name at instantiation. This is done using sed.
*	Add output information to Type	Yann Herklotz	2019-04-18	1	-1/+0
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*	Add output path to each simulator	Yann Herklotz	2019-04-18	1	-4/+6
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*	Update simulator with Result type	Yann Herklotz	2019-04-17	1	-15/+57
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*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	1	-20/+0
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*	Rename Synthesisor -> Synthesiser	Yann Herklotz	2019-04-15	1	-4/+4
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*	Print out local time	Yann Herklotz	2019-04-14	1	-2/+5
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*	Fix the generation of modules and add initialisation	Yann Herklotz	2019-04-10	1	-1/+1
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*	Add Parameter type and remove Description	Yann Herklotz	2019-04-09	1	-2/+2
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*	Fix to the logger	Yann Herklotz	2019-04-03	1	-0/+10
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*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-0/+112