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:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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path:
root
/
src
/
VeriFuzz
/
Sim
/
Quartus.hs
Commit message (
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)
Author
Age
Files
Lines
*
Format files
Yann Herklotz
2019-06-29
1
-4
/
+9
*
Format all files
Yann Herklotz
2019-06-05
1
-1
/
+6
*
Add fix to synthesise correctly with Quartus without MAC
Yann Herklotz
2019-06-02
1
-1
/
+2
*
Remove logging from within tools
Yann Herklotz
2019-05-21
1
-4
/
+1
*
Only compare against the identity synth
Yann Herklotz
2019-05-20
1
-1
/
+1
*
Add NFData to force evaluation of config file
Yann Herklotz
2019-05-09
1
-0
/
+4
*
Add configuration options for all simulators
Yann Herklotz
2019-05-07
1
-6
/
+8
*
Rename some functions to use nicer names
Yann Herklotz
2019-05-07
1
-2
/
+2
*
Formatting files and add result type to front end
Yann Herklotz
2019-04-23
1
-2
/
+8
*
Add new modules to fix Quartus equivalence check
Yann Herklotz
2019-04-21
1
-0
/
+1
*
Add output information to Type
Yann Herklotz
2019-04-18
1
-5
/
+5
*
Add output path to each simulator
Yann Herklotz
2019-04-18
1
-2
/
+6
*
Add Show instances to simulators
Yann Herklotz
2019-04-17
1
-3
/
+7
*
Update simulator with Result type
Yann Herklotz
2019-04-17
1
-13
/
+13
*
Move declaration of SourceInfo
Yann Herklotz
2019-04-15
1
-0
/
+1
*
Rename Synthesisor -> Synthesiser
Yann Herklotz
2019-04-15
1
-1
/
+1
*
Add Quartus implementation
Yann Herklotz
2019-04-14
1
-0
/
+52