| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -1/+1 |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -1/+0 |
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| * | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
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| * | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
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| * | Add Vivado module | Yann Herklotz | 2019-04-03 | 1 | -0/+12 |
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| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+108 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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