| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renaming to VeriSmith | Yann Herklotz | 2019-09-04 | 1 | -133/+0 |
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| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 1 | -10/+10 |
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| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -1/+1 |
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| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 1 | -1/+1 |
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| * | Add part of the simulator implementation | Yann Herklotz | 2019-06-29 | 1 | -5/+19 |
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| * | Remove Maybe from equivalence check | Yann Herklotz | 2019-05-13 | 1 | -6/+5 |
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| * | Use abc for verification | Yann Herklotz | 2019-05-07 | 1 | -1/+1 |
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| * | Add support for multiple modules | Yann Herklotz | 2019-05-07 | 1 | -6/+3 |
| | | | | | | | | Had to manually change module names, as Yosys does not change the module name at instantiation. This is done using sed. | ||||
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+1 |
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| * | Add output information to Type | Yann Herklotz | 2019-04-18 | 1 | -8/+10 |
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| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -1/+1 |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -1/+0 |
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| * | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
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| * | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
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| * | Add Vivado module | Yann Herklotz | 2019-04-03 | 1 | -0/+12 |
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| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+108 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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