index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
VeriFuzz
/
Sim
/
Vivado.hs
Commit message (
Expand
)
Author
Age
Files
Lines
*
Add changes to work with older Vivado
Yann Herklotz
2019-05-26
1
-1
/
+1
*
Remove logging from within tools
Yann Herklotz
2019-05-21
1
-2
/
+0
*
Add NFData to force evaluation of config file
Yann Herklotz
2019-05-09
1
-0
/
+4
*
Add configuration options for all simulators
Yann Herklotz
2019-05-07
1
-12
/
+15
*
Rename some functions to use nicer names
Yann Herklotz
2019-05-07
1
-2
/
+2
*
Add support for multiple modules
Yann Herklotz
2019-05-07
1
-1
/
+1
*
Formatting files and add result type to front end
Yann Herklotz
2019-04-23
1
-1
/
+2
*
Add output information to Type
Yann Herklotz
2019-04-18
1
-5
/
+5
*
Add output path to each simulator
Yann Herklotz
2019-04-18
1
-2
/
+6
*
Add Show instances to simulators
Yann Herklotz
2019-04-17
1
-1
/
+4
*
Update simulator with Result type
Yann Herklotz
2019-04-17
1
-11
/
+14
*
Move declaration of SourceInfo
Yann Herklotz
2019-04-15
1
-0
/
+1
*
Rename Synthesisor -> Synthesiser
Yann Herklotz
2019-04-15
1
-3
/
+3
*
Add quick fix to run without dsp48
Yann Herklotz
2019-04-03
1
-1
/
+2
*
Add Vivado module
Yann Herklotz
2019-04-03
1
-0
/
+48