verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add new maintainer email	Yann Herklotz	2019-07-23	1	-12/+7
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*	Format files	Yann Herklotz	2019-06-29	1	-6/+11
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*	Format all files	Yann Herklotz	2019-06-05	1	-1/+5
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*	Add timeout error to synthesisers	Yann Herklotz	2019-05-25	1	-5/+6
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*	Remove logging from within tools	Yann Herklotz	2019-05-21	1	-8/+2
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*	Format with brittany	Yann Herklotz	2019-05-13	1	-10/+5
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*	Add more reporting to equivalence check	Yann Herklotz	2019-05-13	1	-2/+12
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*	Remove Maybe from equivalence check	Yann Herklotz	2019-05-13	1	-16/+10
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*	Add NFData to force evaluation of config file	Yann Herklotz	2019-05-09	1	-0/+4
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*	Fix unusable UNPACK	Yann Herklotz	2019-05-09	1	-1/+1
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*	Add configuration options for all simulators	Yann Herklotz	2019-05-07	1	-13/+17
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*	Add description field to Yosys	Yann Herklotz	2019-05-07	1	-8/+9
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*	Use abc for verification	Yann Herklotz	2019-05-07	1	-3/+3
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*	Rename some functions to use nicer names	Yann Herklotz	2019-05-07	1	-9/+9
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*	Add support for multiple modules	Yann Herklotz	2019-05-07	1	-2/+3
\| \| \| \| \| \| \|	Had to manually change module names, as Yosys does not change the module name at instantiation. This is done using sed.
*	Formatting files and add result type to front end	Yann Herklotz	2019-04-23	1	-2/+1
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*	Add output information to Type	Yann Herklotz	2019-04-18	1	-11/+10
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*	Add output path to each simulator	Yann Herklotz	2019-04-18	1	-4/+6
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*	Add Show instances to simulators	Yann Herklotz	2019-04-17	1	-1/+4
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*	Fix other type errors and replace with Result type	Yann Herklotz	2019-04-17	1	-24/+33
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*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	1	-0/+1
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*	Rename Synthesisor -> Synthesiser	Yann Herklotz	2019-04-15	1	-4/+4
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*	Fix to the logger	Yann Herklotz	2019-04-03	1	-2/+2
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*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-0/+106