| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 8 | -102/+64 |
| * | Format files | Yann Herklotz | 2019-06-29 | 7 | -80/+141 |
| * | Fix pedantic warnings | Yann Herklotz | 2019-06-29 | 1 | -2/+2 |
| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 2 | -27/+27 |
| * | Add part of the simulator implementation | Yann Herklotz | 2019-06-29 | 2 | -5/+59 |
| * | Format all files | Yann Herklotz | 2019-06-05 | 3 | -3/+17 |
| * | Add fix to synthesise correctly with Quartus without MAC | Yann Herklotz | 2019-06-02 | 1 | -1/+2 |
| * | Add changes to work with older Vivado | Yann Herklotz | 2019-05-26 | 1 | -1/+1 |
| * | Add timeout error to synthesisers | Yann Herklotz | 2019-05-25 | 2 | -12/+20 |
| * | Remove logging from within tools | Yann Herklotz | 2019-05-21 | 5 | -27/+9 |
| * | Only compare against the identity synth | Yann Herklotz | 2019-05-20 | 1 | -1/+1 |
| * | Add renameSource | Yann Herklotz | 2019-05-14 | 1 | -0/+5 |
| * | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -10/+5 |
| * | Add more reporting to equivalence check | Yann Herklotz | 2019-05-13 | 2 | -2/+14 |
| * | Add ResultT to Sh conversion | Yann Herklotz | 2019-05-13 | 1 | -0/+10 |
| * | Remove Maybe from equivalence check | Yann Herklotz | 2019-05-13 | 2 | -22/+15 |
| * | Add NonEmpty to tests | Yann Herklotz | 2019-05-13 | 1 | -2/+1 |
| * | Add Identity to Report | Yann Herklotz | 2019-05-13 | 1 | -1/+9 |
| * | Add Identity synthesiser | Yann Herklotz | 2019-05-13 | 1 | -0/+44 |
| * | Add NFData to force evaluation of config file | Yann Herklotz | 2019-05-09 | 5 | -0/+20 |
| * | Fix unusable UNPACK | Yann Herklotz | 2019-05-09 | 1 | -1/+1 |
| * | Add configuration options for all simulators | Yann Herklotz | 2019-05-07 | 4 | -42/+56 |
| * | Add description field to Yosys | Yann Herklotz | 2019-05-07 | 1 | -8/+9 |
| * | Use abc for verification | Yann Herklotz | 2019-05-07 | 3 | -8/+6 |
| * | Create better command line output | Yann Herklotz | 2019-05-07 | 1 | -1/+8 |
| * | Rename some functions to use nicer names | Yann Herklotz | 2019-05-07 | 6 | -33/+40 |
| * | Add support for multiple modules | Yann Herklotz | 2019-05-07 | 4 | -11/+41 |
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+1 |
| * | Fix XST Synthesis | Yann Herklotz | 2019-04-23 | 1 | -1/+1 |
| * | Formatting files and add result type to front end | Yann Herklotz | 2019-04-23 | 4 | -6/+12 |
| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -0/+1 |
| * | Add output information to Type | Yann Herklotz | 2019-04-18 | 6 | -36/+36 |
| * | Add output path to each simulator | Yann Herklotz | 2019-04-18 | 5 | -13/+28 |
| * | Add Show instances to simulators | Yann Herklotz | 2019-04-17 | 5 | -8/+25 |
| * | Fix other type errors and replace with Result type | Yann Herklotz | 2019-04-17 | 1 | -24/+33 |
| * | Update simulator with Result type | Yann Herklotz | 2019-04-17 | 5 | -61/+111 |
| * | Move Reduce file | Yann Herklotz | 2019-04-17 | 1 | -164/+0 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 6 | -21/+4 |
| * | Rename Synthesisor -> Synthesiser | Yann Herklotz | 2019-04-15 | 5 | -13/+13 |
| * | Replace Env by Fuzz | Yann Herklotz | 2019-04-15 | 1 | -58/+0 |
| * | Change port declarations in Reduce | Yann Herklotz | 2019-04-14 | 1 | -4/+4 |
| * | Print out local time | Yann Herklotz | 2019-04-14 | 1 | -2/+5 |
| * | Add bit vector to Icarus simulation | Yann Herklotz | 2019-04-14 | 1 | -1/+6 |
| * | Add Quartus implementation | Yann Herklotz | 2019-04-14 | 1 | -0/+52 |
| * | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -2/+2 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 4 | -5/+6 |
| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 2 | -4/+4 |
| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -1/+0 |
| * | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
| * | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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