Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add bit vector to Icarus simulation | Yann Herklotz | 2019-04-14 | 1 | -1/+6 |
* | Add Quartus implementation | Yann Herklotz | 2019-04-14 | 1 | -0/+52 |
* | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -2/+2 |
* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 4 | -5/+6 |
* | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 2 | -4/+4 |
* | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -1/+0 |
* | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
* | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
* | Add quick fix to run without dsp48 | Yann Herklotz | 2019-04-03 | 2 | -2/+3 |
* | Add Vivado module | Yann Herklotz | 2019-04-03 | 2 | -0/+60 |
* | Fix to the logger | Yann Herklotz | 2019-04-03 | 5 | -14/+23 |
* | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 7 | -0/+731 |