| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renaming to VeriSmith | Yann Herklotz | 2019-09-04 | 1 | -583/+0 |
| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 1 | -3/+3 |
| * | Add a benchmark | Yann Herklotz | 2019-07-27 | 1 | -34/+61 |
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -11/+7 |
| * | Format files | Yann Herklotz | 2019-06-29 | 1 | -6/+10 |
| * | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 1 | -0/+3 |
| * | Add necessary exports to AST and CodeGen | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Remove modConn lens and replace by modExpr | Yann Herklotz | 2019-05-15 | 1 | -3/+3 |
| * | Use Identifier instead of Text | Yann Herklotz | 2019-05-14 | 1 | -3/+3 |
| * | Add lens to focus on specific module | Yann Herklotz | 2019-05-14 | 1 | -0/+15 |
| * | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -11/+13 |
| * | Use NonEmpty to represent concatenation | Yann Herklotz | 2019-05-13 | 1 | -12/+12 |
| * | Add Plate instance to Statement | Yann Herklotz | 2019-05-11 | 1 | -0/+6 |
| * | Add constant expression to expression conversion and vice versa | Yann Herklotz | 2019-05-10 | 1 | -0/+21 |
| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 1 | -3/+6 |
| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 1 | -0/+2 |
| * | Add support for more event lists | Yann Herklotz | 2019-04-21 | 1 | -0/+3 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 1 | -1/+20 |
| * | Changes to general types | Yann Herklotz | 2019-04-14 | 1 | -95/+86 |
| * | Add for loop to design | Yann Herklotz | 2019-04-12 | 1 | -4/+6 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -0/+2 |
| * | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -1/+1 |
| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -26/+99 |
| * | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 1 | -206/+3 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+617 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 1 | -564/+0 |
| * | Add back Show for tests | Yann Herklotz | 2019-02-01 | 1 | -21/+21 |
| * | [Fix #28] Add Expression generation with context | Yann Herklotz | 2019-02-01 | 1 | -16/+29 |
| * | [Fix #27] Add function to Expr and add Generation type | Yann Herklotz | 2019-02-01 | 1 | -21/+37 |
| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 1 | -2/+10 |
| * | Prettify files | Yann Herklotz | 2019-01-20 | 1 | -0/+2 |
| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 1 | -2/+2 |
| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -11/+7 |
| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 1 | -2/+1 |
| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -38/+97 |
| * | Small improvement to stmnt and expr function | Yann Herklotz | 2019-01-19 | 1 | -13/+16 |
| * | Swap the exports for the types of the AST | Yann Herklotz | 2019-01-19 | 1 | -2/+2 |
| * | Add documentation in AST | Yann Herklotz | 2019-01-10 | 1 | -15/+28 |
| * | Add explicit exports | Yann Herklotz | 2019-01-10 | 1 | -24/+55 |
| * | Derive as many properties as possible | Yann Herklotz | 2019-01-10 | 1 | -30/+21 |
| * | Fix warnings | Yann Herklotz | 2019-01-10 | 1 | -37/+9 |
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 1 | -0/+461 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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