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path: root/src/VeriFuzz/Verilog/AST.hs
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* Add back Show for testsYann Herklotz2019-02-011-21/+21
* [Fix #28] Add Expression generation with contextYann Herklotz2019-02-011-16/+29
* [Fix #27] Add function to Expr and add Generation typeYann Herklotz2019-02-011-21/+37
* [Fix #22] Fix SAT solver equivalence checkingYann Herklotz2019-01-201-2/+10
* Prettify filesYann Herklotz2019-01-201-0/+2
* Rename moduleId to modIdYann Herklotz2019-01-201-2/+2
* Reformat with stylish-haskellYann Herklotz2019-01-191-11/+7
* Add hlint changesYann Herklotz2019-01-191-2/+1
* Add brittany formatting instead of stylish-haskellYann Herklotz2019-01-191-38/+97
* Small improvement to stmnt and expr functionYann Herklotz2019-01-191-13/+16
* Swap the exports for the types of the ASTYann Herklotz2019-01-191-2/+2
* Add documentation in ASTYann Herklotz2019-01-101-15/+28
* Add explicit exportsYann Herklotz2019-01-101-24/+55
* Derive as many properties as possibleYann Herklotz2019-01-101-30/+21
* Fix warningsYann Herklotz2019-01-101-37/+9
* Rename files out of the moduleYann Herklotz2019-01-101-0/+461