verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Reformat with stylish-haskell	Yann Herklotz	2019-01-19	1	-11/+7
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*	Add hlint changes	Yann Herklotz	2019-01-19	1	-2/+1
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*	Add brittany formatting instead of stylish-haskell	Yann Herklotz	2019-01-19	1	-38/+97
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*	Small improvement to stmnt and expr function	Yann Herklotz	2019-01-19	1	-13/+16
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*	Swap the exports for the types of the AST	Yann Herklotz	2019-01-19	1	-2/+2
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*	Add documentation in AST	Yann Herklotz	2019-01-10	1	-15/+28
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*	Add explicit exports	Yann Herklotz	2019-01-10	1	-24/+55
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*	Derive as many properties as possible	Yann Herklotz	2019-01-10	1	-30/+21
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*	Fix warnings	Yann Herklotz	2019-01-10	1	-37/+9
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*	Rename files out of the module	Yann Herklotz	2019-01-10	1	-0/+461