| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -9/+7 |
| * | Format files | Yann Herklotz | 2019-06-29 | 1 | -6/+8 |
| * | Add necessary exports to AST and CodeGen | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -51/+66 |
| * | Use NonEmpty to represent concatenation | Yann Herklotz | 2019-05-13 | 1 | -2/+2 |
| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 1 | -1/+4 |
| * | Add new pretty printer with indentation | Yann Herklotz | 2019-05-09 | 1 | -162/+160 |
| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 1 | -1/+1 |
| * | Format with brittany | Yann Herklotz | 2019-05-05 | 1 | -2/+2 |
| * | Add seeds for reproducible runs | Yann Herklotz | 2019-05-05 | 1 | -1/+1 |
| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 1 | -0/+2 |
| * | Fix code generation for always blocks with or | Yann Herklotz | 2019-04-23 | 1 | -3/+3 |
| * | Add event list generation for always blocks | Yann Herklotz | 2019-04-23 | 1 | -2/+2 |
| * | Add support for more event lists | Yann Herklotz | 2019-04-21 | 1 | -6/+11 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 1 | -1/+0 |
| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -38/+33 |
| * | Add for loop to design | Yann Herklotz | 2019-04-12 | 1 | -9/+9 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -15/+28 |
| * | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -1/+1 |
| * | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 1 | -15/+11 |
| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -29/+50 |
| * | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 1 | -6/+7 |
| * | Better formatting for if-statement | Yann Herklotz | 2019-04-04 | 1 | -2/+2 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+293 |
| * | More restructuring | Yann Herklotz | 2019-02-01 | 1 | -276/+0 |
| * | [Fix #27] Add function to Expr and add Generation type | Yann Herklotz | 2019-02-01 | 1 | -1/+17 |
| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 1 | -1/+7 |
| * | Prettify files | Yann Herklotz | 2019-01-20 | 1 | -0/+2 |
| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 1 | -1/+1 |
| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -8/+6 |
| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 1 | -1/+1 |
| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 1 | -33/+15 |
| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -65/+63 |
| * | Fix all the warnings | Yann Herklotz | 2019-01-10 | 1 | -27/+25 |
| * | Fix warnings | Yann Herklotz | 2019-01-10 | 1 | -2/+2 |
| * | Fix some imports | Yann Herklotz | 2019-01-10 | 1 | -53/+14 |
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 1 | -0/+315 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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