verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Move Gen.hs to Generate.hs	Yann Herklotz	2019-07-26	1	-541/+0
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*	Add non determinism probability to generation	Yann Herklotz	2019-07-26	1	-15/+24
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*	[Fix #52] Correctly resize the modules	Yann Herklotz	2019-07-23	1	-6/+9
\| \| \| \| \|	This was fixed by taking out the clock and wiring it separately as it was shifting all the assignments.
*	Add new maintainer email	Yann Herklotz	2019-07-23	1	-9/+15
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*	Fix the filtering of the local values	Yann Herklotz	2019-07-23	1	-1/+4
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*	Merge branch 'master' into fix/resize-modports	Yann Herklotz	2019-07-21	1	-14/+9
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\| *	Format files	Yann Herklotz	2019-06-29	1	-10/+11
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\| *	Format all files	Yann Herklotz	2019-06-05	1	-4/+5
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\| *	Fix size in output wire	Yann Herklotz	2019-06-05	1	-2/+3
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\| *	Add combination option	Yann Herklotz	2019-06-05	1	-1/+2
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\| *	Remove dead code	Yann Herklotz	2019-06-02	1	-1/+1
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\| *	Add XOR to the output	Yann Herklotz	2019-06-02	1	-1/+1
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\| *	Change parameters of generation	Yann Herklotz	2019-05-22	1	-7/+2
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\| *	Remove unused function	Yann Herklotz	2019-05-21	1	-3/+0
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\| *	Add only identity	Yann Herklotz	2019-05-21	1	-1/+1
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* \|	Multiple initialisations now appearing	Yann Herklotz	2019-07-20	1	-6/+20
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* \|	Fix missing module instantiation	Yann Herklotz	2019-07-09	1	-1/+1
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* \|	Broken fix for modport	Yann Herklotz	2019-05-20	1	-11/+19
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*	Optimisations in the generation	Yann Herklotz	2019-05-14	1	-6/+4
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*	Format with brittany	Yann Herklotz	2019-05-13	1	-5/+9
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*	Use NonEmpty to represent concatenation	Yann Herklotz	2019-05-13	1	-2/+2
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*	Add new pretty printer with indentation	Yann Herklotz	2019-05-09	1	-10/+4
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*	Add combinational and sequential logic support	Yann Herklotz	2019-05-09	1	-30/+5
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*	Support multiple reg assigns in if statements	Yann Herklotz	2019-05-06	1	-19/+18
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*	Modify generation of statements to create more interesting ones	Yann Herklotz	2019-05-05	1	-16/+35
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*	Format with brittany	Yann Herklotz	2019-05-05	1	-12/+26
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*	Add random bit selection for wires	Yann Herklotz	2019-04-26	1	-30/+45
\| \| \| \|	This has not been tested fully yet
*	Fine tune the generation	Yann Herklotz	2019-04-23	1	-15/+13
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*	Add event list generation for always blocks	Yann Herklotz	2019-04-23	1	-1/+2
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*	Add support for more event lists	Yann Herklotz	2019-04-21	1	-1/+27
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*	Reduce the wire size as Quartus was crashing	Yann Herklotz	2019-04-17	1	-1/+9
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*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	1	-6/+7
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*	Format with brittany and add right modules	Yann Herklotz	2019-04-15	1	-11/+11
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*	Add Bit vector instead of using numbers	Yann Herklotz	2019-04-14	1	-58/+57
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*	Fix tests passing	Yann Herklotz	2019-04-13	1	-1/+1
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*	Add for loop to design	Yann Herklotz	2019-04-12	1	-32/+115
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*	Fix the generation of modules and add initialisation	Yann Herklotz	2019-04-10	1	-50/+139
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*	Add probabilities to generation of expressions	Yann Herklotz	2019-04-09	1	-19/+46
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*	Add generation of parameters and constant expressions	Yann Herklotz	2019-04-09	1	-7/+47
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*	Add Parameter type and remove Description	Yann Herklotz	2019-04-09	1	-3/+3
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*	Create Arbitrary module	Yann Herklotz	2019-04-08	1	-0/+1
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*	Generate flip-flops instead of latches	Yann Herklotz	2019-04-06	1	-11/+4
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*	Fix adding port to state and add everything to output	Yann Herklotz	2019-04-04	1	-8/+20
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*	Fix infinite loop in state based generation	Yann Herklotz	2019-04-03	1	-12/+17
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*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-0/+202