Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Modify generation of statements to create more interesting ones | Yann Herklotz | 2019-05-05 | 1 | -16/+35 |
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* | Format with brittany | Yann Herklotz | 2019-05-05 | 1 | -12/+26 |
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* | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 1 | -30/+45 |
| | | | | This has not been tested fully yet | ||||
* | Fine tune the generation | Yann Herklotz | 2019-04-23 | 1 | -15/+13 |
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* | Add event list generation for always blocks | Yann Herklotz | 2019-04-23 | 1 | -1/+2 |
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* | Add support for more event lists | Yann Herklotz | 2019-04-21 | 1 | -1/+27 |
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* | Reduce the wire size as Quartus was crashing | Yann Herklotz | 2019-04-17 | 1 | -1/+9 |
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* | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 1 | -6/+7 |
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* | Format with brittany and add right modules | Yann Herklotz | 2019-04-15 | 1 | -11/+11 |
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* | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -58/+57 |
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* | Fix tests passing | Yann Herklotz | 2019-04-13 | 1 | -1/+1 |
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* | Add for loop to design | Yann Herklotz | 2019-04-12 | 1 | -32/+115 |
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* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -50/+139 |
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* | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -19/+46 |
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* | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 1 | -7/+47 |
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* | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -3/+3 |
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* | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 1 | -0/+1 |
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* | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -11/+4 |
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* | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
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* | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 1 | -12/+17 |
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* | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+202 |