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path: root/src/VeriFuzz/Verilog/Gen.hs
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* Move Gen.hs to Generate.hsYann Herklotz2019-07-261-541/+0
* Add non determinism probability to generationYann Herklotz2019-07-261-15/+24
* [Fix #52] Correctly resize the modulesYann Herklotz2019-07-231-6/+9
* Add new maintainer emailYann Herklotz2019-07-231-9/+15
* Fix the filtering of the local valuesYann Herklotz2019-07-231-1/+4
* Merge branch 'master' into fix/resize-modportsYann Herklotz2019-07-211-14/+9
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| * Format filesYann Herklotz2019-06-291-10/+11
| * Format all filesYann Herklotz2019-06-051-4/+5
| * Fix size in output wireYann Herklotz2019-06-051-2/+3
| * Add combination optionYann Herklotz2019-06-051-1/+2
| * Remove dead codeYann Herklotz2019-06-021-1/+1
| * Add XOR to the outputYann Herklotz2019-06-021-1/+1
| * Change parameters of generationYann Herklotz2019-05-221-7/+2
| * Remove unused functionYann Herklotz2019-05-211-3/+0
| * Add only identityYann Herklotz2019-05-211-1/+1
* | Multiple initialisations now appearingYann Herklotz2019-07-201-6/+20
* | Fix missing module instantiationYann Herklotz2019-07-091-1/+1
* | Broken fix for modportYann Herklotz2019-05-201-11/+19
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* Optimisations in the generationYann Herklotz2019-05-141-6/+4
* Format with brittanyYann Herklotz2019-05-131-5/+9
* Use NonEmpty to represent concatenationYann Herklotz2019-05-131-2/+2
* Add new pretty printer with indentationYann Herklotz2019-05-091-10/+4
* Add combinational and sequential logic supportYann Herklotz2019-05-091-30/+5
* Support multiple reg assigns in if statementsYann Herklotz2019-05-061-19/+18
* Modify generation of statements to create more interesting onesYann Herklotz2019-05-051-16/+35
* Format with brittanyYann Herklotz2019-05-051-12/+26
* Add random bit selection for wiresYann Herklotz2019-04-261-30/+45
* Fine tune the generationYann Herklotz2019-04-231-15/+13
* Add event list generation for always blocksYann Herklotz2019-04-231-1/+2
* Add support for more event listsYann Herklotz2019-04-211-1/+27
* Reduce the wire size as Quartus was crashingYann Herklotz2019-04-171-1/+9
* Move declaration of SourceInfoYann Herklotz2019-04-151-6/+7
* Format with brittany and add right modulesYann Herklotz2019-04-151-11/+11
* Add Bit vector instead of using numbersYann Herklotz2019-04-141-58/+57
* Fix tests passingYann Herklotz2019-04-131-1/+1
* Add for loop to designYann Herklotz2019-04-121-32/+115
* Fix the generation of modules and add initialisationYann Herklotz2019-04-101-50/+139
* Add probabilities to generation of expressionsYann Herklotz2019-04-091-19/+46
* Add generation of parameters and constant expressionsYann Herklotz2019-04-091-7/+47
* Add Parameter type and remove DescriptionYann Herklotz2019-04-091-3/+3
* Create Arbitrary moduleYann Herklotz2019-04-081-0/+1
* Generate flip-flops instead of latchesYann Herklotz2019-04-061-11/+4
* Fix adding port to state and add everything to outputYann Herklotz2019-04-041-8/+20
* Fix infinite loop in state based generationYann Herklotz2019-04-031-12/+17
* Large refactor with passing testsYann Herklotz2019-04-021-0/+202