| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 1 | -0/+1 |
| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -11/+4 |
| * | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
| * | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 1 | -12/+17 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+202 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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