Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add for loop to design | Yann Herklotz | 2019-04-12 | 1 | -32/+115 |
* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -50/+139 |
* | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -19/+46 |
* | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 1 | -7/+47 |
* | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -3/+3 |
* | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 1 | -0/+1 |
* | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -11/+4 |
* | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
* | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 1 | -12/+17 |
* | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+202 |