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:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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path:
root
/
src
/
VeriFuzz
/
Verilog
/
Gen.hs
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Author
Age
Files
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*
Move declaration of SourceInfo
Yann Herklotz
2019-04-15
1
-6
/
+7
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*
Format with brittany and add right modules
Yann Herklotz
2019-04-15
1
-11
/
+11
|
*
Add Bit vector instead of using numbers
Yann Herklotz
2019-04-14
1
-58
/
+57
|
*
Fix tests passing
Yann Herklotz
2019-04-13
1
-1
/
+1
|
*
Add for loop to design
Yann Herklotz
2019-04-12
1
-32
/
+115
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*
Fix the generation of modules and add initialisation
Yann Herklotz
2019-04-10
1
-50
/
+139
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*
Add probabilities to generation of expressions
Yann Herklotz
2019-04-09
1
-19
/
+46
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*
Add generation of parameters and constant expressions
Yann Herklotz
2019-04-09
1
-7
/
+47
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*
Add Parameter type and remove Description
Yann Herklotz
2019-04-09
1
-3
/
+3
|
*
Create Arbitrary module
Yann Herklotz
2019-04-08
1
-0
/
+1
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*
Generate flip-flops instead of latches
Yann Herklotz
2019-04-06
1
-11
/
+4
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*
Fix adding port to state and add everything to output
Yann Herklotz
2019-04-04
1
-8
/
+20
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*
Fix infinite loop in state based generation
Yann Herklotz
2019-04-03
1
-12
/
+17
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*
Large refactor with passing tests
Yann Herklotz
2019-04-02
1
-0
/
+202