| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renaming to VeriSmith | Yann Herklotz | 2019-09-04 | 1 | -93/+0 |
| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 1 | -4/+4 |
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -2/+2 |
| * | Format files | Yann Herklotz | 2019-06-29 | 1 | -1/+1 |
| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -20/+13 |
| * | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -7/+7 |
| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -3/+4 |
| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -6/+6 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+99 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |