| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renaming to VeriSmith | Yann Herklotz | 2019-09-04 | 1 | -401/+0 |
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| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 1 | -14/+14 |
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| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -29/+26 |
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| * | Format files | Yann Herklotz | 2019-06-29 | 1 | -22/+24 |
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| * | Format all files | Yann Herklotz | 2019-06-05 | 1 | -1/+8 |
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| * | Add combination option | Yann Herklotz | 2019-06-05 | 1 | -3/+3 |
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| * | Add XOR to the output | Yann Herklotz | 2019-06-02 | 1 | -1/+2 |
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| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 1 | -0/+4 |
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| * | Add Mutation class in Mutate.hs | Yann Herklotz | 2019-05-11 | 1 | -1/+99 |
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| * | Fix some of the doctests in Mutate.hs | Yann Herklotz | 2019-05-10 | 1 | -5/+5 |
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| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 1 | -0/+2 |
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| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 1 | -0/+4 |
| | | | | | This has not been tested fully yet | ||||
| * | Fix tests and remove Parser tests for now | Yann Herklotz | 2019-04-17 | 1 | -5/+5 |
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| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -31/+29 |
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| * | Fix tests passing | Yann Herklotz | 2019-04-13 | 1 | -1/+1 |
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| * | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -8/+12 |
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| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -10/+18 |
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| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -4/+4 |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 1 | -2/+1 |
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| * | New combine function | Yann Herklotz | 2019-04-04 | 1 | -0/+5 |
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| * | Export Vivado types and fix test failure | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
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| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+272 |
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| * | More restructuring | Yann Herklotz | 2019-02-01 | 1 | -169/+0 |
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| * | [Fix #24] Small changes and looked at always block output | Yann Herklotz | 2019-02-01 | 1 | -7/+9 |
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| * | Make code a bit more readable | Yann Herklotz | 2019-02-01 | 1 | -1/+2 |
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| * | Remove extra import | Yann Herklotz | 2019-02-01 | 1 | -1/+0 |
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| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 1 | -1/+23 |
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| * | Prettify files | Yann Herklotz | 2019-01-20 | 1 | -0/+7 |
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| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 1 | -5/+5 |
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| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -3/+1 |
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| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 1 | -1/+1 |
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| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 1 | -26/+7 |
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| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 1 | -51/+62 |
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| * | Fix all the warnings | Yann Herklotz | 2019-01-10 | 1 | -2/+2 |
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| * | Fix documentation error | Yann Herklotz | 2019-01-10 | 1 | -1/+1 |
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| * | Fix warnings | Yann Herklotz | 2019-01-10 | 1 | -34/+34 |
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| * | Add render to test | Yann Herklotz | 2019-01-10 | 1 | -3/+3 |
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| * | Fix warnings | Yann Herklotz | 2019-01-10 | 1 | -1/+1 |
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| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 1 | -0/+148 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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