Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -55/+62 |
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* | Change the arguments to Text in the Parser | Yann Herklotz | 2019-05-13 | 1 | -6/+26 |
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* | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 1 | -13/+77 |
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* | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 1 | -7/+118 |
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* | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -16/+9 |
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* | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -1/+1 |
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* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -3/+3 |
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* | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -1/+1 |
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* | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -4/+2 |
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* | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 1 | -6/+8 |
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* | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+316 |