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path: root/src/VeriFuzz/Verilog
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* Format all filesYann Herklotz2019-06-052-5/+13
* Fix size in output wireYann Herklotz2019-06-051-2/+3
* Add combination optionYann Herklotz2019-06-052-4/+5
* Remove dead codeYann Herklotz2019-06-021-1/+1
* Add XOR to the outputYann Herklotz2019-06-022-2/+3
* Fix used wire check for clkYann Herklotz2019-05-241-0/+3
* Change parameters of generationYann Herklotz2019-05-221-7/+2
* Add necessary exports to AST and CodeGenYann Herklotz2019-05-212-2/+2
* Remove unused functionYann Herklotz2019-05-211-3/+0
* Add only identityYann Herklotz2019-05-211-1/+1
* Remove modConn lens and replace by modExprYann Herklotz2019-05-151-3/+3
* Use Identifier instead of TextYann Herklotz2019-05-141-3/+3
* Optimisations in the generationYann Herklotz2019-05-141-6/+4
* Add lens to focus on specific moduleYann Herklotz2019-05-141-0/+15
* Format with brittanyYann Herklotz2019-05-135-128/+157
* Use NonEmpty to represent concatenationYann Herklotz2019-05-133-16/+16
* Change the arguments to Text in the ParserYann Herklotz2019-05-132-8/+28
* Add Quote.hsYann Herklotz2019-05-121-0/+49
* Implement module item reduction properlyYann Herklotz2019-05-112-1/+8
* Add Plate instance to StatementYann Herklotz2019-05-111-0/+6
* Add Mutation class in Mutate.hsYann Herklotz2019-05-111-1/+99
* Fixed parser to parse all the generated verilogYann Herklotz2019-05-101-13/+77
* Add always and initial blocks to parserYann Herklotz2019-05-101-7/+118
* Fix some of the doctests in Mutate.hsYann Herklotz2019-05-101-5/+5
* Add constant expression to expression conversion and vice versaYann Herklotz2019-05-101-0/+21
* Add new pretty printer with indentationYann Herklotz2019-05-092-172/+164
* Add reduction strategy for modulesYann Herklotz2019-05-093-4/+9
* Add combinational and sequential logic supportYann Herklotz2019-05-091-30/+5
* Support multiple reg assigns in if statementsYann Herklotz2019-05-061-19/+18
* Modify generation of statements to create more interesting onesYann Herklotz2019-05-051-16/+35
* Format with brittanyYann Herklotz2019-05-053-25/+38
* Add seeds for reproducible runsYann Herklotz2019-05-051-1/+1
* Add random bit selection for wiresYann Herklotz2019-04-265-34/+74
* Fix code generation for always blocks with orYann Herklotz2019-04-231-3/+3
* Fine tune the generationYann Herklotz2019-04-231-15/+13
* Add event list generation for always blocksYann Herklotz2019-04-232-3/+4
* Add support for more event listsYann Herklotz2019-04-213-7/+41
* Reduce the wire size as Quartus was crashingYann Herklotz2019-04-171-1/+9
* Fix tests and remove Parser tests for nowYann Herklotz2019-04-171-5/+5
* Move declaration of SourceInfoYann Herklotz2019-04-153-8/+27
* Format with brittany and add right modulesYann Herklotz2019-04-152-16/+16
* Add Bit vector instead of using numbersYann Herklotz2019-04-145-163/+141
* Changes to general typesYann Herklotz2019-04-141-95/+86
* Add Eval module to evaluate expressionsYann Herklotz2019-04-141-0/+103
* Add BitVec type to model Verilog bit vectorsYann Herklotz2019-04-141-0/+115
* Fix tests passingYann Herklotz2019-04-132-2/+2
* Remove Arbitrary modelYann Herklotz2019-04-121-226/+0
* Add for loop to designYann Herklotz2019-04-123-45/+130
* Change Port type to include lower boundYann Herklotz2019-04-123-16/+20
* Fix the generation of modules and add initialisationYann Herklotz2019-04-107-90/+204