verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Use HashMap for contextfeature/hashmap	Yann Herklotz	2019-07-29	2	-120/+2
*	Add a benchmark	Yann Herklotz	2019-07-27	2	-35/+66
*	Move Gen.hs to Generate.hs	Yann Herklotz	2019-07-26	1	-541/+0
*	Add non determinism probability to generation	Yann Herklotz	2019-07-26	1	-15/+24
*	[Fix #52] Correctly resize the modules	Yann Herklotz	2019-07-23	1	-6/+9
*	Add new maintainer email	Yann Herklotz	2019-07-23	11	-84/+78
*	Fix the filtering of the local values	Yann Herklotz	2019-07-23	1	-1/+4
*	Merge branch 'master' into fix/resize-modports	Yann Herklotz	2019-07-21	8	-69/+86
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\| *	Format files	Yann Herklotz	2019-06-29	8	-60/+72
\| *	Format all files	Yann Herklotz	2019-06-05	2	-5/+13
\| *	Fix size in output wire	Yann Herklotz	2019-06-05	1	-2/+3
\| *	Add combination option	Yann Herklotz	2019-06-05	2	-4/+5
\| *	Remove dead code	Yann Herklotz	2019-06-02	1	-1/+1
\| *	Add XOR to the output	Yann Herklotz	2019-06-02	2	-2/+3
\| *	Fix used wire check for clk	Yann Herklotz	2019-05-24	1	-0/+3
\| *	Change parameters of generation	Yann Herklotz	2019-05-22	1	-7/+2
\| *	Add necessary exports to AST and CodeGen	Yann Herklotz	2019-05-21	2	-2/+2
\| *	Remove unused function	Yann Herklotz	2019-05-21	1	-3/+0
\| *	Add only identity	Yann Herklotz	2019-05-21	1	-1/+1
* \|	Multiple initialisations now appearing	Yann Herklotz	2019-07-20	1	-6/+20
* \|	Fix missing module instantiation	Yann Herklotz	2019-07-09	1	-1/+1
* \|	Broken fix for modport	Yann Herklotz	2019-05-20	1	-11/+19
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*	Remove modConn lens and replace by modExpr	Yann Herklotz	2019-05-15	1	-3/+3
*	Use Identifier instead of Text	Yann Herklotz	2019-05-14	1	-3/+3
*	Optimisations in the generation	Yann Herklotz	2019-05-14	1	-6/+4
*	Add lens to focus on specific module	Yann Herklotz	2019-05-14	1	-0/+15
*	Format with brittany	Yann Herklotz	2019-05-13	5	-128/+157
*	Use NonEmpty to represent concatenation	Yann Herklotz	2019-05-13	3	-16/+16
*	Change the arguments to Text in the Parser	Yann Herklotz	2019-05-13	2	-8/+28
*	Add Quote.hs	Yann Herklotz	2019-05-12	1	-0/+49
*	Implement module item reduction properly	Yann Herklotz	2019-05-11	2	-1/+8
*	Add Plate instance to Statement	Yann Herklotz	2019-05-11	1	-0/+6
*	Add Mutation class in Mutate.hs	Yann Herklotz	2019-05-11	1	-1/+99
*	Fixed parser to parse all the generated verilog	Yann Herklotz	2019-05-10	1	-13/+77
*	Add always and initial blocks to parser	Yann Herklotz	2019-05-10	1	-7/+118
*	Fix some of the doctests in Mutate.hs	Yann Herklotz	2019-05-10	1	-5/+5
*	Add constant expression to expression conversion and vice versa	Yann Herklotz	2019-05-10	1	-0/+21
*	Add new pretty printer with indentation	Yann Herklotz	2019-05-09	2	-172/+164
*	Add reduction strategy for modules	Yann Herklotz	2019-05-09	3	-4/+9
*	Add combinational and sequential logic support	Yann Herklotz	2019-05-09	1	-30/+5
*	Support multiple reg assigns in if statements	Yann Herklotz	2019-05-06	1	-19/+18
*	Modify generation of statements to create more interesting ones	Yann Herklotz	2019-05-05	1	-16/+35
*	Format with brittany	Yann Herklotz	2019-05-05	3	-25/+38
*	Add seeds for reproducible runs	Yann Herklotz	2019-05-05	1	-1/+1
*	Add random bit selection for wires	Yann Herklotz	2019-04-26	5	-34/+74
*	Fix code generation for always blocks with or	Yann Herklotz	2019-04-23	1	-3/+3
*	Fine tune the generation	Yann Herklotz	2019-04-23	1	-15/+13
*	Add event list generation for always blocks	Yann Herklotz	2019-04-23	2	-3/+4
*	Add support for more event lists	Yann Herklotz	2019-04-21	3	-7/+41
*	Reduce the wire size as Quartus was crashing	Yann Herklotz	2019-04-17	1	-1/+9