| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 3 | -8/+27 | |
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| * | Format with brittany and add right modules | Yann Herklotz | 2019-04-15 | 2 | -16/+16 | |
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| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 5 | -163/+141 | |
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| * | Changes to general types | Yann Herklotz | 2019-04-14 | 1 | -95/+86 | |
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| * | Add Eval module to evaluate expressions | Yann Herklotz | 2019-04-14 | 1 | -0/+103 | |
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| * | Add BitVec type to model Verilog bit vectors | Yann Herklotz | 2019-04-14 | 1 | -0/+115 | |
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| * | Fix tests passing | Yann Herklotz | 2019-04-13 | 2 | -2/+2 | |
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| * | Remove Arbitrary model | Yann Herklotz | 2019-04-12 | 1 | -226/+0 | |
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| * | Add for loop to design | Yann Herklotz | 2019-04-12 | 3 | -45/+130 | |
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| * | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 3 | -16/+20 | |
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| * | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 7 | -90/+204 | |
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| * | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 5 | -35/+50 | |
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| * | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 3 | -22/+60 | |
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| * | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 8 | -83/+192 | |
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| * | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 4 | -212/+232 | |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 2 | -13/+5 | |
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| * | New combine function | Yann Herklotz | 2019-04-04 | 1 | -0/+5 | |
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| * | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 | |
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| * | Better formatting for if-statement | Yann Herklotz | 2019-04-04 | 1 | -2/+2 | |
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| * | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 1 | -12/+17 | |
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| * | Export Vivado types and fix test failure | Yann Herklotz | 2019-04-03 | 1 | -1/+1 | |
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| * | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 1 | -6/+8 | |
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| * | Formatting file | Yann Herklotz | 2019-04-03 | 1 | -92/+92 | |
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| * | Add emacs mode line to Lex.x | Yann Herklotz | 2019-04-02 | 1 | -0/+1 | |
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| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 9 | -0/+2444 | |
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| * | More restructuring | Yann Herklotz | 2019-02-01 | 4 | -1081/+0 | |
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| * | Add back Show for tests | Yann Herklotz | 2019-02-01 | 1 | -21/+21 | |
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| * | [Fix #28] Add Expression generation with context | Yann Herklotz | 2019-02-01 | 1 | -16/+29 | |
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| * | [Fix #27] Add function to Expr and add Generation type | Yann Herklotz | 2019-02-01 | 2 | -22/+54 | |
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| * | [Fix #24] Small changes and looked at always block output | Yann Herklotz | 2019-02-01 | 1 | -7/+9 | |
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| * | Make code a bit more readable | Yann Herklotz | 2019-02-01 | 1 | -1/+2 | |
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| * | Remove extra import | Yann Herklotz | 2019-02-01 | 1 | -1/+0 | |
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| * | [Fix #22] Fix SAT solver equivalence checking | Yann Herklotz | 2019-01-20 | 3 | -4/+40 | |
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| * | Prettify files | Yann Herklotz | 2019-01-20 | 3 | -0/+11 | |
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| * | Rename moduleId to modId | Yann Herklotz | 2019-01-20 | 4 | -9/+12 | |
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| * | Reformat with stylish-haskell | Yann Herklotz | 2019-01-19 | 4 | -23/+15 | |
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| * | Add hlint changes | Yann Herklotz | 2019-01-19 | 3 | -4/+3 | |
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| * | Set column to 100 | Yann Herklotz | 2019-01-19 | 3 | -62/+23 | |
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| * | Add brittany formatting instead of stylish-haskell | Yann Herklotz | 2019-01-19 | 4 | -162/+230 | |
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| * | Small improvement to stmnt and expr function | Yann Herklotz | 2019-01-19 | 1 | -13/+16 | |
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| * | Swap the exports for the types of the AST | Yann Herklotz | 2019-01-19 | 1 | -2/+2 | |
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| * | Fix all the warnings | Yann Herklotz | 2019-01-10 | 3 | -31/+28 | |
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| * | Add documentation in AST | Yann Herklotz | 2019-01-10 | 1 | -15/+28 | |
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| * | Fix documentation error | Yann Herklotz | 2019-01-10 | 1 | -1/+1 | |
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| * | Add explicit exports | Yann Herklotz | 2019-01-10 | 1 | -24/+55 | |
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| * | Fix warnings | Yann Herklotz | 2019-01-10 | 2 | -36/+36 | |
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| * | Derive as many properties as possible | Yann Herklotz | 2019-01-10 | 1 | -30/+21 | |
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| * | Fix some imports | Yann Herklotz | 2019-01-10 | 1 | -53/+14 | |
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| * | Add render to test | Yann Herklotz | 2019-01-10 | 1 | -3/+3 | |
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| * | Remove Arbitrary.hs | Yann Herklotz | 2019-01-10 | 1 | -70/+0 | |
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 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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