index
:
verismith
dev/distance
dev/reducer
develop
feature/hashmap
feature/ignored-constructs
feature/nondeterminism
feature/update-dependencies
fix/remove-DRBG
master
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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VeriFuzz
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Verilog
Commit message (
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Author
Age
Files
Lines
*
Format with brittany
Yann Herklotz
2019-05-13
5
-128
/
+157
*
Use NonEmpty to represent concatenation
Yann Herklotz
2019-05-13
3
-16
/
+16
*
Change the arguments to Text in the Parser
Yann Herklotz
2019-05-13
2
-8
/
+28
*
Add Quote.hs
Yann Herklotz
2019-05-12
1
-0
/
+49
*
Implement module item reduction properly
Yann Herklotz
2019-05-11
2
-1
/
+8
*
Add Plate instance to Statement
Yann Herklotz
2019-05-11
1
-0
/
+6
*
Add Mutation class in Mutate.hs
Yann Herklotz
2019-05-11
1
-1
/
+99
*
Fixed parser to parse all the generated verilog
Yann Herklotz
2019-05-10
1
-13
/
+77
*
Add always and initial blocks to parser
Yann Herklotz
2019-05-10
1
-7
/
+118
*
Fix some of the doctests in Mutate.hs
Yann Herklotz
2019-05-10
1
-5
/
+5
*
Add constant expression to expression conversion and vice versa
Yann Herklotz
2019-05-10
1
-0
/
+21
*
Add new pretty printer with indentation
Yann Herklotz
2019-05-09
2
-172
/
+164
*
Add reduction strategy for modules
Yann Herklotz
2019-05-09
3
-4
/
+9
*
Add combinational and sequential logic support
Yann Herklotz
2019-05-09
1
-30
/
+5
*
Support multiple reg assigns in if statements
Yann Herklotz
2019-05-06
1
-19
/
+18
*
Modify generation of statements to create more interesting ones
Yann Herklotz
2019-05-05
1
-16
/
+35
*
Format with brittany
Yann Herklotz
2019-05-05
3
-25
/
+38
*
Add seeds for reproducible runs
Yann Herklotz
2019-05-05
1
-1
/
+1
*
Add random bit selection for wires
Yann Herklotz
2019-04-26
5
-34
/
+74
*
Fix code generation for always blocks with or
Yann Herklotz
2019-04-23
1
-3
/
+3
*
Fine tune the generation
Yann Herklotz
2019-04-23
1
-15
/
+13
*
Add event list generation for always blocks
Yann Herklotz
2019-04-23
2
-3
/
+4
*
Add support for more event lists
Yann Herklotz
2019-04-21
3
-7
/
+41
*
Reduce the wire size as Quartus was crashing
Yann Herklotz
2019-04-17
1
-1
/
+9
*
Fix tests and remove Parser tests for now
Yann Herklotz
2019-04-17
1
-5
/
+5
*
Move declaration of SourceInfo
Yann Herklotz
2019-04-15
3
-8
/
+27
*
Format with brittany and add right modules
Yann Herklotz
2019-04-15
2
-16
/
+16
*
Add Bit vector instead of using numbers
Yann Herklotz
2019-04-14
5
-163
/
+141
*
Changes to general types
Yann Herklotz
2019-04-14
1
-95
/
+86
*
Add Eval module to evaluate expressions
Yann Herklotz
2019-04-14
1
-0
/
+103
*
Add BitVec type to model Verilog bit vectors
Yann Herklotz
2019-04-14
1
-0
/
+115
*
Fix tests passing
Yann Herklotz
2019-04-13
2
-2
/
+2
*
Remove Arbitrary model
Yann Herklotz
2019-04-12
1
-226
/
+0
*
Add for loop to design
Yann Herklotz
2019-04-12
3
-45
/
+130
*
Change Port type to include lower bound
Yann Herklotz
2019-04-12
3
-16
/
+20
*
Fix the generation of modules and add initialisation
Yann Herklotz
2019-04-10
7
-90
/
+204
*
Add probabilities to generation of expressions
Yann Herklotz
2019-04-09
5
-35
/
+50
*
Add generation of parameters and constant expressions
Yann Herklotz
2019-04-09
3
-22
/
+60
*
Add Parameter type and remove Description
Yann Herklotz
2019-04-09
8
-83
/
+192
*
Create Arbitrary module
Yann Herklotz
2019-04-08
4
-212
/
+232
*
Generate flip-flops instead of latches
Yann Herklotz
2019-04-06
2
-13
/
+5
*
New combine function
Yann Herklotz
2019-04-04
1
-0
/
+5
*
Fix adding port to state and add everything to output
Yann Herklotz
2019-04-04
1
-8
/
+20
*
Better formatting for if-statement
Yann Herklotz
2019-04-04
1
-2
/
+2
*
Fix infinite loop in state based generation
Yann Herklotz
2019-04-03
1
-12
/
+17
*
Export Vivado types and fix test failure
Yann Herklotz
2019-04-03
1
-1
/
+1
*
Apply brittany to modified modules
Yann Herklotz
2019-04-03
1
-6
/
+8
*
Formatting file
Yann Herklotz
2019-04-03
1
-92
/
+92
*
Add emacs mode line to Lex.x
Yann Herklotz
2019-04-02
1
-0
/
+1
*
Large refactor with passing tests
Yann Herklotz
2019-04-02
9
-0
/
+2444
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