Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Format all files | Yann Herklotz | 2019-06-05 | 2 | -5/+13 |
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* | Fix size in output wire | Yann Herklotz | 2019-06-05 | 1 | -2/+3 |
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* | Add combination option | Yann Herklotz | 2019-06-05 | 2 | -4/+5 |
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* | Remove dead code | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
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* | Add XOR to the output | Yann Herklotz | 2019-06-02 | 2 | -2/+3 |
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* | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 1 | -0/+3 |
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* | Change parameters of generation | Yann Herklotz | 2019-05-22 | 1 | -7/+2 |
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* | Add necessary exports to AST and CodeGen | Yann Herklotz | 2019-05-21 | 2 | -2/+2 |
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* | Remove unused function | Yann Herklotz | 2019-05-21 | 1 | -3/+0 |
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* | Add only identity | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
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* | Remove modConn lens and replace by modExpr | Yann Herklotz | 2019-05-15 | 1 | -3/+3 |
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* | Use Identifier instead of Text | Yann Herklotz | 2019-05-14 | 1 | -3/+3 |
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* | Optimisations in the generation | Yann Herklotz | 2019-05-14 | 1 | -6/+4 |
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* | Add lens to focus on specific module | Yann Herklotz | 2019-05-14 | 1 | -0/+15 |
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* | Format with brittany | Yann Herklotz | 2019-05-13 | 5 | -128/+157 |
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* | Use NonEmpty to represent concatenation | Yann Herklotz | 2019-05-13 | 3 | -16/+16 |
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* | Change the arguments to Text in the Parser | Yann Herklotz | 2019-05-13 | 2 | -8/+28 |
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* | Add Quote.hs | Yann Herklotz | 2019-05-12 | 1 | -0/+49 |
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* | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 2 | -1/+8 |
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* | Add Plate instance to Statement | Yann Herklotz | 2019-05-11 | 1 | -0/+6 |
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* | Add Mutation class in Mutate.hs | Yann Herklotz | 2019-05-11 | 1 | -1/+99 |
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* | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 1 | -13/+77 |
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* | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 1 | -7/+118 |
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* | Fix some of the doctests in Mutate.hs | Yann Herklotz | 2019-05-10 | 1 | -5/+5 |
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* | Add constant expression to expression conversion and vice versa | Yann Herklotz | 2019-05-10 | 1 | -0/+21 |
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* | Add new pretty printer with indentation | Yann Herklotz | 2019-05-09 | 2 | -172/+164 |
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* | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 3 | -4/+9 |
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* | Add combinational and sequential logic support | Yann Herklotz | 2019-05-09 | 1 | -30/+5 |
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* | Support multiple reg assigns in if statements | Yann Herklotz | 2019-05-06 | 1 | -19/+18 |
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* | Modify generation of statements to create more interesting ones | Yann Herklotz | 2019-05-05 | 1 | -16/+35 |
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* | Format with brittany | Yann Herklotz | 2019-05-05 | 3 | -25/+38 |
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* | Add seeds for reproducible runs | Yann Herklotz | 2019-05-05 | 1 | -1/+1 |
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* | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 5 | -34/+74 |
| | | | | This has not been tested fully yet | ||||
* | Fix code generation for always blocks with or | Yann Herklotz | 2019-04-23 | 1 | -3/+3 |
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* | Fine tune the generation | Yann Herklotz | 2019-04-23 | 1 | -15/+13 |
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* | Add event list generation for always blocks | Yann Herklotz | 2019-04-23 | 2 | -3/+4 |
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* | Add support for more event lists | Yann Herklotz | 2019-04-21 | 3 | -7/+41 |
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* | Reduce the wire size as Quartus was crashing | Yann Herklotz | 2019-04-17 | 1 | -1/+9 |
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* | Fix tests and remove Parser tests for now | Yann Herklotz | 2019-04-17 | 1 | -5/+5 |
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* | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 3 | -8/+27 |
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* | Format with brittany and add right modules | Yann Herklotz | 2019-04-15 | 2 | -16/+16 |
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* | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 5 | -163/+141 |
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* | Changes to general types | Yann Herklotz | 2019-04-14 | 1 | -95/+86 |
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* | Add Eval module to evaluate expressions | Yann Herklotz | 2019-04-14 | 1 | -0/+103 |
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* | Add BitVec type to model Verilog bit vectors | Yann Herklotz | 2019-04-14 | 1 | -0/+115 |
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* | Fix tests passing | Yann Herklotz | 2019-04-13 | 2 | -2/+2 |
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* | Remove Arbitrary model | Yann Herklotz | 2019-04-12 | 1 | -226/+0 |
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* | Add for loop to design | Yann Herklotz | 2019-04-12 | 3 | -45/+130 |
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* | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 3 | -16/+20 |
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* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 7 | -90/+204 |
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