verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[Fix #28] Add Expression generation with context	Yann Herklotz	2019-02-01	1	-16/+29
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*	[Fix #27] Add function to Expr and add Generation type	Yann Herklotz	2019-02-01	2	-22/+54
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*	[Fix #24] Small changes and looked at always block output	Yann Herklotz	2019-02-01	1	-7/+9
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*	Make code a bit more readable	Yann Herklotz	2019-02-01	1	-1/+2
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*	Remove extra import	Yann Herklotz	2019-02-01	1	-1/+0
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*	[Fix #22] Fix SAT solver equivalence checking	Yann Herklotz	2019-01-20	3	-4/+40
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*	Prettify files	Yann Herklotz	2019-01-20	3	-0/+11
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*	Rename moduleId to modId	Yann Herklotz	2019-01-20	4	-9/+12
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*	Reformat with stylish-haskell	Yann Herklotz	2019-01-19	4	-23/+15
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*	Add hlint changes	Yann Herklotz	2019-01-19	3	-4/+3
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*	Set column to 100	Yann Herklotz	2019-01-19	3	-62/+23
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*	Add brittany formatting instead of stylish-haskell	Yann Herklotz	2019-01-19	4	-162/+230
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*	Small improvement to stmnt and expr function	Yann Herklotz	2019-01-19	1	-13/+16
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*	Swap the exports for the types of the AST	Yann Herklotz	2019-01-19	1	-2/+2
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*	Fix all the warnings	Yann Herklotz	2019-01-10	3	-31/+28
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*	Add documentation in AST	Yann Herklotz	2019-01-10	1	-15/+28
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*	Fix documentation error	Yann Herklotz	2019-01-10	1	-1/+1
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*	Add explicit exports	Yann Herklotz	2019-01-10	1	-24/+55
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*	Fix warnings	Yann Herklotz	2019-01-10	2	-36/+36
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*	Derive as many properties as possible	Yann Herklotz	2019-01-10	1	-30/+21
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*	Fix some imports	Yann Herklotz	2019-01-10	1	-53/+14
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*	Add render to test	Yann Herklotz	2019-01-10	1	-3/+3
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*	Remove Arbitrary.hs	Yann Herklotz	2019-01-10	1	-70/+0
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*	Fix warnings	Yann Herklotz	2019-01-10	3	-44/+13
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*	Rename remaining modules	Yann Herklotz	2019-01-10	1	-169/+55
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*	Rename files out of the module	Yann Herklotz	2019-01-10	5	-0/+1183