| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix pedantic warnings | Yann Herklotz | 2019-06-29 | 5 | -10/+21 |
| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 3 | -48/+55 |
| * | Add part of the simulator implementation | Yann Herklotz | 2019-06-29 | 3 | -5/+104 |
| * | Format all files | Yann Herklotz | 2019-06-05 | 9 | -84/+117 |
| * | Fix size in output wire | Yann Herklotz | 2019-06-05 | 1 | -2/+3 |
| * | Add combination option | Yann Herklotz | 2019-06-05 | 3 | -5/+10 |
| * | Add median and mean sampling | Yann Herklotz | 2019-06-02 | 1 | -10/+39 |
| * | Remove dead code | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
| * | Add XOR to the output | Yann Herklotz | 2019-06-02 | 2 | -2/+3 |
| * | Add fix to synthesise correctly with Quartus without MAC | Yann Herklotz | 2019-06-02 | 1 | -1/+2 |
| * | Add check for quicker reduction | Yann Herklotz | 2019-06-02 | 1 | -17/+19 |
| * | Add check for synthfails | Yann Herklotz | 2019-05-30 | 1 | -1/+2 |
| * | Add changes to work with older Vivado | Yann Herklotz | 2019-05-26 | 1 | -1/+1 |
| * | Fix reduction for statements | Yann Herklotz | 2019-05-25 | 2 | -12/+16 |
| * | Export helpers from Fuzz.hs | Yann Herklotz | 2019-05-25 | 1 | -0/+3 |
| * | Use synthesiser instance | Yann Herklotz | 2019-05-25 | 1 | -1/+1 |
| * | Add synthesis fails to fuzzer | Yann Herklotz | 2019-05-25 | 2 | -0/+17 |
| * | Add reducesynthesis function | Yann Herklotz | 2019-05-25 | 1 | -0/+13 |
| * | Add timeout error to synthesisers | Yann Herklotz | 2019-05-25 | 2 | -12/+20 |
| * | No expression reduction | Yann Herklotz | 2019-05-24 | 1 | -1/+1 |
| * | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 3 | -14/+26 |
| * | Reduction throws away path if it finds a passing one | Yann Herklotz | 2019-05-24 | 2 | -21/+18 |
| * | Change parameters of generation | Yann Herklotz | 2019-05-22 | 1 | -7/+2 |
| * | Add hat sampling to config | Yann Herklotz | 2019-05-22 | 1 | -2/+4 |
| * | Add choice for hat sampling in config | Yann Herklotz | 2019-05-21 | 1 | -6/+14 |
| * | Add necessary exports to AST and CodeGen | Yann Herklotz | 2019-05-21 | 2 | -2/+2 |
| * | Add lines of code to report | Yann Herklotz | 2019-05-21 | 1 | -3/+11 |
| * | Add hat sampling | Yann Herklotz | 2019-05-21 | 1 | -18/+40 |
| * | Add a different State and new FuzzReport output | Yann Herklotz | 2019-05-21 | 1 | -43/+112 |
| * | Add more fields to the FuzzReport | Yann Herklotz | 2019-05-21 | 1 | -34/+145 |
| * | Switch meaning of Semigroup | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Remove unused function | Yann Herklotz | 2019-05-21 | 1 | -3/+0 |
| * | Remove logging from within tools | Yann Herklotz | 2019-05-21 | 5 | -27/+9 |
| * | Add only identity | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Fix warning on CI | Yann Herklotz | 2019-05-20 | 1 | -2/+2 |
| * | Format using brittany | Yann Herklotz | 2019-05-20 | 1 | -1/+5 |
| * | Only compare against the identity synth | Yann Herklotz | 2019-05-20 | 2 | -3/+4 |
| * | Change simple graph check to acyclic check | Yann Herklotz | 2019-05-19 | 2 | -27/+40 |
| * | Add colour to the report | Yann Herklotz | 2019-05-18 | 1 | -32/+35 |
| * | Add ability to clean up verilog file | Yann Herklotz | 2019-05-15 | 1 | -3/+115 |
| * | Remove modConn lens and replace by modExpr | Yann Herklotz | 2019-05-15 | 2 | -4/+3 |
| * | Use Identifier instead of Text | Yann Herklotz | 2019-05-14 | 1 | -3/+3 |
| * | Add cleaning on all modules | Yann Herklotz | 2019-05-14 | 1 | -17/+24 |
| * | Add reduction for multiple modules | Yann Herklotz | 2019-05-14 | 1 | -29/+72 |
| * | Optimisations in the generation | Yann Herklotz | 2019-05-14 | 1 | -6/+4 |
| * | Add lens to focus on specific module | Yann Herklotz | 2019-05-14 | 1 | -0/+15 |
| * | Add renameSource | Yann Herklotz | 2019-05-14 | 1 | -0/+5 |
| * | Format with brittany | Yann Herklotz | 2019-05-13 | 10 | -321/+352 |
| * | Fix report generation for fuzz run | Yann Herklotz | 2019-05-13 | 1 | -3/+10 |
| * | Add more reporting to equivalence check | Yann Herklotz | 2019-05-13 | 3 | -8/+22 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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