verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add template file	Yann Herklotz	2019-01-20	4	-47/+72
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*	Rename moduleId to modId	Yann Herklotz	2019-01-20	7	-22/+33
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*	Reformat with stylish-haskell	Yann Herklotz	2019-01-19	15	-87/+70
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*	Add hlint changes	Yann Herklotz	2019-01-19	3	-4/+3
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*	Set column to 100	Yann Herklotz	2019-01-19	9	-83/+31
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*	Add brittany formatting instead of stylish-haskell	Yann Herklotz	2019-01-19	16	-289/+385
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*	Small improvement to stmnt and expr function	Yann Herklotz	2019-01-19	1	-13/+16
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*	Swap the exports for the types of the AST	Yann Herklotz	2019-01-19	1	-2/+2
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*	Inline the timeout function	Yann Herklotz	2019-01-19	1	-0/+2
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*	Fix all the warnings	Yann Herklotz	2019-01-10	8	-47/+37
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*	Add documentation in AST	Yann Herklotz	2019-01-10	1	-15/+28
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*	Fix documentation error	Yann Herklotz	2019-01-10	1	-1/+1
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*	Add explicit exports	Yann Herklotz	2019-01-10	1	-24/+55
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*	Fix warnings	Yann Herklotz	2019-01-10	4	-51/+38
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*	Remove Arbitrary from main module	Yann Herklotz	2019-01-10	1	-2/+0
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*	Derive as many properties as possible	Yann Herklotz	2019-01-10	1	-30/+21
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*	Fix some imports	Yann Herklotz	2019-01-10	1	-53/+14
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*	Add render to test	Yann Herklotz	2019-01-10	1	-3/+3
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*	Remove Arbitrary.hs	Yann Herklotz	2019-01-10	1	-70/+0
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*	Fix warnings	Yann Herklotz	2019-01-10	3	-44/+13
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*	Rename remaining modules	Yann Herklotz	2019-01-10	3	-191/+77
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*	Rename files out of the module	Yann Herklotz	2019-01-10	18	-0/+1824