| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add option to drop reg and wire from output | Yann Herklotz | 2020-04-09 | 1 | -0/+4 |
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| * | Remove DRBG dependency | Yann Herklotz | 2020-04-07 | 1 | -16/+3 |
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| * | Add annotations and make it compile again | Yann Herklotz | 2020-04-07 | 1 | -4/+4 |
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| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -4/+4 |
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| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
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| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
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| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 1 | -6/+6 |
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| * | Fix build | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
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| * | Add cross-check between netlists | Yann Herklotz | 2019-11-24 | 1 | -2/+2 |
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| * | Add counter example parsing | Yann Herklotz | 2019-11-10 | 1 | -17/+17 |
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| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 1 | -3/+10 |
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| * | Add parsing of existing rtl when starting fuzz run | Yann Herklotz | 2019-10-31 | 1 | -2/+8 |
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| * | Add data-file installation path | Yann Herklotz | 2019-10-29 | 1 | -5/+14 |
| | | | | | | This removes the need to recursively copy the data directory which will also save on space. | ||||
| * | Add --no-reduction | Yann Herklotz | 2019-10-28 | 1 | -2/+3 |
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| * | Add OptParser to separate option parsing | Yann Herklotz | 2019-10-27 | 1 | -245/+4 |
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| * | Add -k functionality | Yann Herklotz | 2019-10-18 | 1 | -2/+2 |
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| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 1 | -3/+3 |
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| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+553 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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