| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Format with ormolu | Yann Herklotz | 2020-05-12 | 1 | -390/+446 |
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| * | Fix types with annotations | Yann Herklotz | 2020-05-11 | 1 | -1/+1 |
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| * | Add option to drop reg and wire from output | Yann Herklotz | 2020-04-09 | 1 | -16/+46 |
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| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
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| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
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| * | Add configuration for default Yosys location | Yann Herklotz | 2019-12-26 | 1 | -1/+7 |
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| * | Update documentation | Yann Herklotz | 2019-12-26 | 1 | -26/+49 |
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| * | Support proper Quartus Pro version | Yann Herklotz | 2019-11-14 | 1 | -11/+19 |
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| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 1 | -4/+4 |
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| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+496 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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