verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	WIP changes to the AST types	Yann Herklotz	2020-03-16	1	-9/+9
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*	Update license notices	Yann Herklotz	2020-01-06	1	-1/+1
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*	Update license to dual license GPLv3	Yann Herklotz	2020-01-06	1	-1/+1
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*	Add configuration for default Yosys location	Yann Herklotz	2019-12-26	1	-5/+8
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*	Do not run counter example if no rerunner is specified	Yann Herklotz	2019-12-03	1	-8/+13
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*	More minimisation	Yann Herklotz	2019-12-03	1	-3/+9
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*	Add output of v file during reduction	Yann Herklotz	2019-11-24	1	-22/+4
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*	Show the result as it is run	Yann Herklotz	2019-11-24	1	-4/+4
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*	Add cross-check between netlists	Yann Herklotz	2019-11-24	1	-9/+11
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*	Fix counter-example simulation run	Yann Herklotz	2019-11-24	1	-1/+1
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*	Add reduction for simulation failures	Yann Herklotz	2019-11-12	1	-12/+55
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*	Add counter example parsing	Yann Herklotz	2019-11-10	1	-2/+2
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*	Add data-file installation path	Yann Herklotz	2019-10-29	1	-13/+16
\| \| \| \| \|	This removes the need to recursively copy the data directory which will also save on space.
*	Run simulation on all tools passing synthesis	Yann Herklotz	2019-10-28	1	-20/+27
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*	Add mtl dependency to enable easier use of transformers	Yann Herklotz	2019-10-27	1	-104/+140
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*	Change location of the html reports	Yann Herklotz	2019-10-18	1	-3/+5
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*	Add -k functionality	Yann Herklotz	2019-10-18	1	-4/+26
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*	Rename Sim to Tool	Yann Herklotz	2019-10-18	1	-21/+16
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*	[Fix #63] Make build pass again	Yann Herklotz	2019-10-06	1	-9/+5
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*	Rename main modules	Yann Herklotz	2019-09-18	1	-0/+466