| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add data-file installation path | Yann Herklotz | 2019-10-29 | 1 | -13/+16 |
| | | | | | | This removes the need to recursively copy the data directory which will also save on space. | ||||
| * | Run simulation on all tools passing synthesis | Yann Herklotz | 2019-10-28 | 1 | -20/+27 |
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| * | Add mtl dependency to enable easier use of transformers | Yann Herklotz | 2019-10-27 | 1 | -104/+140 |
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| * | Change location of the html reports | Yann Herklotz | 2019-10-18 | 1 | -3/+5 |
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| * | Add -k functionality | Yann Herklotz | 2019-10-18 | 1 | -4/+26 |
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| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 1 | -21/+16 |
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| * | [Fix #63] Make build pass again | Yann Herklotz | 2019-10-06 | 1 | -9/+5 |
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| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+466 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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