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path: root/src/Verismith/Verilog
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* Fix distance always giving 0dev/distanceYann Herklotz2020-05-051-7/+7
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* Add distance to commandlineYann Herklotz2020-04-261-1/+15
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* Add more distance measures for ASTYann Herklotz2020-04-261-16/+82
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* Add distance measure for lists with testcasesYann Herklotz2020-04-261-0/+87
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* Add distance functionYann Herklotz2020-04-251-0/+14
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* Add annotations and make it compile againYann Herklotz2020-04-071-0/+4
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* WIP changes to the AST typesYann Herklotz2020-03-166-70/+71
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* Changes to AST to support annotationsYann Herklotz2020-03-041-289/+305
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* Fix spacing in the generated VerilogYann Herklotz2020-03-031-16/+20
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* Add case statement to the ASTYann Herklotz2020-03-032-1/+41
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* Update license noticesYann Herklotz2020-01-0610-10/+10
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* Update license to dual license GPLv3Yann Herklotz2020-01-0610-10/+10
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* Add ModConnNamed in testbenchYann Herklotz2019-11-241-1/+1
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* Fix more changes to for loopsYann Herklotz2019-11-241-1/+1
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* Do not mutate the expression in the for loopYann Herklotz2019-11-241-1/+1
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* Add reduction pass to remove constants from concatYann Herklotz2019-11-051-0/+6
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* Add comment to code generationYann Herklotz2019-10-251-1/+1
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* Rename main modulesYann Herklotz2019-09-1811-0/+2866