| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Changes to AST to support annotations | Yann Herklotz | 2020-03-04 | 1 | -289/+305 |
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| * | Fix spacing in the generated Verilog | Yann Herklotz | 2020-03-03 | 1 | -16/+20 |
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| * | Add case statement to the AST | Yann Herklotz | 2020-03-03 | 2 | -1/+41 |
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| * | Update license notices | Yann Herklotz | 2020-01-06 | 10 | -10/+10 |
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| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 10 | -10/+10 |
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| * | Add ModConnNamed in testbench | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
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| * | Fix more changes to for loops | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
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| * | Do not mutate the expression in the for loop | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
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| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 1 | -0/+6 |
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| * | Add comment to code generation | Yann Herklotz | 2019-10-25 | 1 | -1/+1 |
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| * | Rename main modules | Yann Herklotz | 2019-09-18 | 11 | -0/+2866 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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