verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add ability to clean up verilog file	Yann Herklotz	2019-05-15	1	-3/+115
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*	Remove modConn lens and replace by modExpr	Yann Herklotz	2019-05-15	2	-4/+3
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*	Use Identifier instead of Text	Yann Herklotz	2019-05-14	1	-3/+3
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*	Add cleaning on all modules	Yann Herklotz	2019-05-14	1	-17/+24
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*	Add reduction for multiple modules	Yann Herklotz	2019-05-14	1	-29/+72
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*	Optimisations in the generation	Yann Herklotz	2019-05-14	1	-6/+4
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*	Add lens to focus on specific module	Yann Herklotz	2019-05-14	1	-0/+15
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*	Add renameSource	Yann Herklotz	2019-05-14	1	-0/+5
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*	Format with brittany	Yann Herklotz	2019-05-13	11	-361/+403
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*	Fix report generation for fuzz run	Yann Herklotz	2019-05-13	1	-3/+10
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*	Add more reporting to equivalence check	Yann Herklotz	2019-05-13	3	-8/+22
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*	Add optimisation to check if at bottom	Yann Herklotz	2019-05-13	1	-17/+40
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*	Add Identity to synthesisers	Yann Herklotz	2019-05-13	1	-0/+5
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*	Add reduction to fuzz run	Yann Herklotz	2019-05-13	2	-3/+34
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*	Add html output for report	Yann Herklotz	2019-05-13	1	-15/+54
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*	Inverse case statement	Yann Herklotz	2019-05-13	1	-3/+3
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*	Add ResultT to Sh conversion	Yann Herklotz	2019-05-13	2	-2/+12
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*	Add reducer function for two arbitrary Synthesiser	Yann Herklotz	2019-05-13	1	-4/+13
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*	Remove Maybe from equivalence check	Yann Herklotz	2019-05-13	3	-23/+16
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*	Add NonEmpty to tests	Yann Herklotz	2019-05-13	3	-6/+5
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*	Add Identity to Report	Yann Herklotz	2019-05-13	2	-23/+48
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*	Add reduction for the commandline	Yann Herklotz	2019-05-13	2	-43/+97
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*	Use NonEmpty to represent concatenation	Yann Herklotz	2019-05-13	3	-16/+16
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*	Change the arguments to Text in the Parser	Yann Herklotz	2019-05-13	2	-8/+28
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*	Add Identity synthesiser	Yann Herklotz	2019-05-13	1	-0/+44
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*	Add randomisation of config file with --randomise	Yann Herklotz	2019-05-12	1	-5/+55
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*	Remove warnings	Yann Herklotz	2019-05-12	1	-118/+119
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*	Add defaultMain	Yann Herklotz	2019-05-12	1	-1/+243
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*	Add Quote.hs	Yann Herklotz	2019-05-12	1	-0/+49
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*	Add working statement reduction	Yann Herklotz	2019-05-12	1	-30/+60
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*	Implement module item reduction properly	Yann Herklotz	2019-05-11	3	-6/+18
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*	Fix warnings for CI	Yann Herklotz	2019-05-11	1	-3/+3
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*	Add Plate instance to Statement	Yann Herklotz	2019-05-11	1	-0/+6
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*	Add Mutation class in Mutate.hs	Yann Herklotz	2019-05-11	1	-1/+99
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*	Add Quote export to main module	Yann Herklotz	2019-05-11	1	-0/+3
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*	Add new reduction techniques	Yann Herklotz	2019-05-11	1	-121/+93
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*	Fixed parser to parse all the generated verilog	Yann Herklotz	2019-05-10	2	-20/+84
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*	Add always and initial blocks to parser	Yann Herklotz	2019-05-10	1	-7/+118
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*	Fix some of the doctests in Mutate.hs	Yann Herklotz	2019-05-10	1	-5/+5
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*	Add constant expression to expression conversion and vice versa	Yann Herklotz	2019-05-10	2	-0/+23
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*	Fix but remove the doctests for now	Yann Herklotz	2019-05-10	1	-25/+25
\| \| \| \| \|	They were not working well with the current printing method. I have to find a way to remove the spaces from the output.
*	Add new pretty printer with indentation	Yann Herklotz	2019-05-09	4	-185/+177
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*	Add reduction strategy for modules	Yann Herklotz	2019-05-09	5	-16/+166
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*	Add NFData to force evaluation of config file	Yann Herklotz	2019-05-09	9	-167/+101
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*	Fix unusable UNPACK	Yann Herklotz	2019-05-09	1	-1/+1
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*	Add combinational and sequential logic support	Yann Herklotz	2019-05-09	3	-97/+55
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*	Only show the seed	Yann Herklotz	2019-05-07	1	-3/+1
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*	Add configuration options for all simulators	Yann Herklotz	2019-05-07	7	-66/+213
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*	Add description field to Yosys	Yann Herklotz	2019-05-07	3	-14/+13
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*	Use abc for verification	Yann Herklotz	2019-05-07	3	-8/+6
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