verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Restructure and add tests	Yann Herklotz	2018-11-30	1	-19/+0
*	Add lens library and extend types for AST	Yann Herklotz	2018-11-30	1	-5/+65
*	Add AST to the exported modules	Yann Herklotz	2018-11-30	1	-0/+3
*	Add some simplifications (map -> fmap)	Yann Herklotz	2018-11-29	1	-5/+6
*	Add Verilog AST	Yann Herklotz	2018-11-29	1	-0/+13
*	Improve generation	Yann Herklotz	2018-11-16	1	-15/+15
*	Basic generation with errors	Yann Herklotz	2018-11-16	3	-6/+24
*	Remove Nor and Nand from types	Yann Herklotz	2018-11-16	1	-4/+2
*	Format and remove unnecessary declarations	Yann Herklotz	2018-11-16	1	-6/+3
*	Add statements to the Verilog module	Yann Herklotz	2018-11-16	1	-12/+24
*	Add style to the files	Yann Herklotz	2018-11-14	5	-24/+23
*	Add testbench to the end	Yann Herklotz	2018-11-09	1	-1/+1
*	Generate some Verilog code from graph	Yann Herklotz	2018-11-09	2	-9/+38
*	Random generation of DAG	Yann Herklotz	2018-11-09	4	-34/+46
*	Add main module	Yann Herklotz	2018-11-09	1	-0/+13
*	Add initial module files	Yann Herklotz	2018-11-09	3	-0/+22
*	Add simple verilog AND gate	Yann Herklotz	2018-11-07	1	-1/+1
*	Generate random undirected graph	Yann Herklotz	2018-11-05	1	-29/+20
*	Simple visualization	Yann Herklotz	2018-10-29	1	-18/+7
*	Add case to make it more readable	Yann Herklotz	2018-10-29	1	-5/+10
*	Partial tree visualization	Yann Herklotz	2018-10-29	1	-1/+2
*	Broken change rendering the graph	Yann Herklotz	2018-10-29	1	-2/+16
*	Random generation of trees	Yann Herklotz	2018-10-28	1	-8/+18
*	Initial commit	Yann Herklotz	2018-10-28	1	-0/+28