| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add Eval module to evaluate expressions | Yann Herklotz | 2019-04-14 | 1 | -0/+103 |
| * | Add BitVec type to model Verilog bit vectors | Yann Herklotz | 2019-04-14 | 1 | -0/+115 |
| * | Add Quartus implementation | Yann Herklotz | 2019-04-14 | 1 | -0/+52 |
| * | Merge branch 'docs' | Yann Herklotz | 2019-04-13 | 2 | -0/+12 |
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| | * | Add partial documentation | Yann Herklotz | 2019-04-07 | 2 | -0/+12 |
| * | | Fix tests passing | Yann Herklotz | 2019-04-13 | 2 | -2/+2 |
| * | | Add recursion schemes implementation | Yann Herklotz | 2019-04-13 | 1 | -0/+84 |
| * | | Remove Arbitrary model | Yann Herklotz | 2019-04-12 | 1 | -226/+0 |
| * | | Add for loop to design | Yann Herklotz | 2019-04-12 | 4 | -46/+135 |
| * | | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 6 | -25/+24 |
| * | | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 14 | -169/+289 |
| * | | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 7 | -37/+51 |
| * | | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 3 | -22/+60 |
| * | | Add more configuration options | Yann Herklotz | 2019-04-09 | 1 | -31/+125 |
| * | | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 15 | -95/+204 |
| * | | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 5 | -213/+234 |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 3 | -14/+5 |
| * | New combine function | Yann Herklotz | 2019-04-04 | 1 | -0/+5 |
| * | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
| * | Better formatting for if-statement | Yann Herklotz | 2019-04-04 | 1 | -2/+2 |
| * | Reorganise runEquivalence | Yann Herklotz | 2019-04-04 | 1 | -5/+10 |
| * | Fix for latches in design | Yann Herklotz | 2019-04-04 | 1 | -0/+1 |
| * | Add verilog modules to equivalence checking | Yann Herklotz | 2019-04-03 | 1 | -1/+1 |
| * | Fix infinite loop in state based generation | Yann Herklotz | 2019-04-03 | 2 | -13/+18 |
| * | Generate Verilog instead of ModDecl | Yann Herklotz | 2019-04-03 | 1 | -2/+2 |
| * | Add quick fix to run without dsp48 | Yann Herklotz | 2019-04-03 | 2 | -2/+3 |
| * | Export Vivado types and fix test failure | Yann Herklotz | 2019-04-03 | 3 | -6/+10 |
| * | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 2 | -12/+19 |
| * | Add Vivado module | Yann Herklotz | 2019-04-03 | 2 | -0/+60 |
| * | Fix to the logger | Yann Herklotz | 2019-04-03 | 5 | -14/+23 |
| * | Formatting file | Yann Herklotz | 2019-04-03 | 1 | -92/+92 |
| * | Add emacs mode line to Lex.x | Yann Herklotz | 2019-04-02 | 1 | -0/+1 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 26 | -256/+503 |
| * | Rename to Verilog | Yann Herklotz | 2019-04-02 | 12 | -40/+42 |
| * | Fix hlint hints | Yann Herklotz | 2019-04-02 | 2 | -7/+8 |
| * | Add more configuration options and small fix | Yann Herklotz | 2019-04-02 | 2 | -13/+31 |
| * | Remove Hedgehog from modulev0.2.0.0 | Yann Herklotz | 2019-04-02 | 1 | -8/+6 |
| * | Add conditionals to config | Yann Herklotz | 2019-04-02 | 1 | -1/+5 |
| * | Make GenVerilog part of Arb | Yann Herklotz | 2019-04-02 | 1 | -3/+2 |
| * | Fix Circuit types | Yann Herklotz | 2019-04-02 | 1 | -5/+4 |
| * | Switch all the types from Arbitrary to Arb | Yann Herklotz | 2019-04-02 | 1 | -208/+223 |
| * | Switch to Hedgehog in graph and verilog generation | Yann Herklotz | 2019-04-02 | 2 | -39/+39 |
| * | Fix random generation for Circuit | Yann Herklotz | 2019-04-02 | 1 | -19/+29 |
| * | Remove fgl-arbitrary completely | Yann Herklotz | 2019-04-02 | 1 | -25/+0 |
| * | Run through brittany | Yann Herklotz | 2019-04-01 | 6 | -184/+199 |
| * | Fix warnings in code | Yann Herklotz | 2019-03-31 | 2 | -25/+7 |
| * | Fix some of the tests | Yann Herklotz | 2019-03-31 | 1 | -1/+2 |
| * | Rewrite the parser with real lexer | Yann Herklotz | 2019-03-31 | 8 | -579/+970 |
| * | Add documentation | Yann Herklotz | 2019-03-30 | 1 | -10/+28 |
| * | Add if statement type | Yann Herklotz | 2019-03-30 | 1 | -0/+4 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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