verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
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*	[Fix #17] Add size to ports	Yann Herklotz	2018-12-31	2	-5/+13
*	Add doctest test	Yann Herklotz	2018-12-31	1	-0/+8
*	[Fix #13, Fix #15] Fix type errors and add inst functions	Yann Herklotz	2018-12-30	4	-14/+17
*	Change modPort type from Maybe to List	Yann Herklotz	2018-12-30	1	-1/+1
*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	4	-14/+23
*	Move helper functions	Yann Herklotz	2018-12-30	3	-5/+7
*	Add remove duplicates	Yann Herklotz	2018-12-29	2	-6/+18
*	Add internal function for fix	Yann Herklotz	2018-12-29	1	-0/+6
*	Fix verilog output for output port	Yann Herklotz	2018-12-29	1	-1/+1
*	Add alternative generation method	Yann Herklotz	2018-12-29	1	-0/+29
*	Add new generation method	Yann Herklotz	2018-12-29	1	-14/+14
*	Style changes	Yann Herklotz	2018-12-29	1	-7/+7
*	Make generation more controlled	Yann Herklotz	2018-12-29	1	-2/+4
*	Rearrange instances	Yann Herklotz	2018-12-29	1	-5/+5
*	Changes to the API	Yann Herklotz	2018-12-29	5	-43/+60
*	Add simulator code	Yann Herklotz	2018-12-29	3	-8/+24
*	Fix documentation and copyright	Yann Herklotz	2018-12-28	17	-51/+51
*	Add simulator module	Yann Herklotz	2018-12-28	5	-0/+215
*	Fix imports and cabal file	Yann Herklotz	2018-12-28	3	-16/+13
*	Move verilog files into specific module	Yann Herklotz	2018-12-28	4	-21/+104
*	Add instantiation function	Yann Herklotz	2018-12-27	1	-2/+7
*	Remove OverloadedStrings in favour of declaration in module	Yann Herklotz	2018-12-27	5	-10/+1
*	Format fixes	Yann Herklotz	2018-12-27	1	-20/+20
*	Small style change	Yann Herklotz	2018-12-27	1	-1/+1
*	Improve expression and statement generation	Yann Herklotz	2018-12-27	1	-20/+96
*	Add documentation to main module	Yann Herklotz	2018-12-25	1	-0/+13
*	Add code generation for new types	Yann Herklotz	2018-12-25	1	-20/+130
*	Type fixes	Yann Herklotz	2018-12-25	1	-7/+8
*	Rename Node to Int	Yann Herklotz	2018-12-25	1	-1/+1
*	[Close #10, Fix #12] Add Mutations for wires	Yann Herklotz	2018-12-25	1	-7/+13
*	Add more types	Yann Herklotz	2018-12-25	1	-41/+181
*	Add Helpers.hs	Yann Herklotz	2018-12-25	1	-0/+75
*	Fix nesting, generation broken for nested groups	Yann Herklotz	2018-12-23	1	-3/+17
*	Add nesting to the SourceText	Yann Herklotz	2018-12-23	1	-1/+16
*	[Fix #11] Implement the traversal	Yann Herklotz	2018-12-23	1	-18/+32
*	Start implementing the nesting functionality	Yann Herklotz	2018-12-23	1	-2/+23
*	Derive `Eq` for the Verilog AST.	Yann Herklotz	2018-12-22	2	-13/+14
*	Add unimplemented nestId function	Yann Herklotz	2018-12-22	1	-0/+4
*	Add Mutate module to VeriFuzz	Yann Herklotz	2018-12-22	2	-0/+17
*	Format ASTGen	Yann Herklotz	2018-12-22	1	-6/+3
*	[Fix #2] Add generation of AST from Circuit	Yann Herklotz	2018-12-22	4	-19/+33
*	Add shared code to code generation	Yann Herklotz	2018-12-22	1	-0/+34
*	Add more functions to the code generation	Yann Herklotz	2018-12-22	2	-25/+21
*	Add more AST generation	Yann Herklotz	2018-12-20	1	-1/+19
*	Fix documentation	Yann Herklotz	2018-12-15	5	-15/+117
*	Add new imports	Yann Herklotz	2018-12-15	1	-3/+5
*	Add AST generation	Yann Herklotz	2018-12-15	1	-0/+47
*	Rename types to circuit	Yann Herklotz	2018-12-15	1	-1/+15
*	[Fix #1] Fix the negative number generation	Yann Herklotz	2018-12-04	2	-2/+5
*	[Fix #8] Add Circuit newtype	Yann Herklotz	2018-12-02	1	-0/+3