verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Rename remaining modules	Yann Herklotz	2019-01-10	4	-205/+91
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*	Rename files out of the module	Yann Herklotz	2019-01-10	19	-0/+0
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*	Rename module names so that I can move them	Yann Herklotz	2019-01-10	15	-183/+315
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*	Add show instance to Identifier	Yann Herklotz	2019-01-09	1	-4/+8
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*	Fix Xst synthesis	Yann Herklotz	2019-01-09	1	-5/+11
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*	Small improvements to Icarus	Yann Herklotz	2019-01-09	1	-7/+12
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*	[Fix #19] Add support for equivalence checking	Yann Herklotz	2019-01-09	1	-7/+42
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*	[Fix #20] Add more examples and finish makeTop	Yann Herklotz	2019-01-09	1	-0/+31
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*	Change to timeout to support FilePath	Yann Herklotz	2019-01-09	1	-4/+4
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*	Make generated wires longer	Yann Herklotz	2019-01-09	1	-3/+5
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*	Finish the testbenck for Icarus	Yann Herklotz	2019-01-02	1	-2/+18
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*	Add conversion ByteString -> Integer	Yann Herklotz	2019-01-02	1	-3/+2
\| \| \| \|	This means that the integer can then be printed in hex using showHex.
*	Add num instance for the delay	Yann Herklotz	2019-01-02	1	-0/+9
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*	Fix indentation	Yann Herklotz	2019-01-02	1	-10/+10
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*	Remove Monoid instance for LVal, as it does not quite fit	Yann Herklotz	2019-01-01	1	-9/+0
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*	Add bsToI function	Yann Herklotz	2019-01-01	1	-5/+8
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*	Add helper function to turn port into expr	Yann Herklotz	2019-01-01	1	-0/+3
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*	Add monoid instance for LVal	Yann Herklotz	2019-01-01	1	-1/+10
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*	Fix Monoid instance for Expr	Yann Herklotz	2019-01-01	1	-1/+1
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*	Add back monoid instance for statement	Yann Herklotz	2019-01-01	1	-0/+3
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*	Fix logic in CodeGen with maybe	Yann Herklotz	2019-01-01	1	-2/+4
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*	Fix linting warnings	Yann Herklotz	2019-01-01	8	-16/+14
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*	Formatting	Yann Herklotz	2019-01-01	1	-3/+3
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*	Remove empty statement and Monoid instance	Yann Herklotz	2019-01-01	1	-4/+0
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*	Fix Semigroup instances	Yann Herklotz	2019-01-01	1	-4/+8
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*	Use Monoid Statement instance to make code more concise	Yann Herklotz	2019-01-01	1	-5/+3
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*	Add documentation	Yann Herklotz	2019-01-01	1	-0/+10
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*	Add string instance to expression	Yann Herklotz	2019-01-01	1	-12/+42
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*	Add missing case in function	Yann Herklotz	2018-12-31	1	-0/+2
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*	Add show instance and add concat to reglval	Yann Herklotz	2018-12-31	4	-42/+88
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*	Fix build errors	Yann Herklotz	2018-12-31	2	-2/+5
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*	Remove sep and fromList in favour of fold	Yann Herklotz	2018-12-31	3	-26/+7
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*	Separate arbitrary from types	Yann Herklotz	2018-12-31	1	-0/+184
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*	Adding code to Icarus	Yann Herklotz	2018-12-31	1	-3/+15
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*	Large refactor	Yann Herklotz	2018-12-31	7	-326/+149
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*	Finish module instantiation	Yann Herklotz	2018-12-31	2	-5/+16
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*	Add direction to Decl and add doctest	Yann Herklotz	2018-12-31	4	-11/+26
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*	[Fix #17] Add size to ports	Yann Herklotz	2018-12-31	2	-5/+13
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*	Add doctest test	Yann Herklotz	2018-12-31	1	-0/+8
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*	[Fix #13, Fix #15] Fix type errors and add inst functions	Yann Herklotz	2018-12-30	4	-14/+17
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*	Change modPort type from Maybe to List	Yann Herklotz	2018-12-30	1	-1/+1
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*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	4	-14/+23
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*	Move helper functions	Yann Herklotz	2018-12-30	3	-5/+7
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*	Add remove duplicates	Yann Herklotz	2018-12-29	2	-6/+18
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*	Add internal function for fix	Yann Herklotz	2018-12-29	1	-0/+6
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*	Fix verilog output for output port	Yann Herklotz	2018-12-29	1	-1/+1
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*	Add alternative generation method	Yann Herklotz	2018-12-29	1	-0/+29
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*	Add new generation method	Yann Herklotz	2018-12-29	1	-14/+14
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*	Style changes	Yann Herklotz	2018-12-29	1	-7/+7
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*	Make generation more controlled	Yann Herklotz	2018-12-29	1	-2/+4
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