verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add documentation to Config.hs	Yann Herklotz	2019-04-23	1	-16/+128
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*	Fix some errors in the templates	Yann Herklotz	2019-04-23	1	-0/+1
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*	Fix XST Synthesis	Yann Herklotz	2019-04-23	1	-1/+1
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*	Add simulator support to the config file	Yann Herklotz	2019-04-23	2	-179/+101
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*	Formatting files and add result type to front end	Yann Herklotz	2019-04-23	5	-6/+14
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*	Fix code generation for always blocks with or	Yann Herklotz	2019-04-23	1	-3/+3
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*	Fine tune the generation	Yann Herklotz	2019-04-23	1	-15/+13
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*	Add Report type	Yann Herklotz	2019-04-23	1	-0/+169
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*	Add event list generation for always blocks	Yann Herklotz	2019-04-23	3	-73/+4
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*	Add support for more event lists	Yann Herklotz	2019-04-21	4	-11/+74
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*	Add new modules to fix Quartus equivalence check	Yann Herklotz	2019-04-21	1	-0/+1
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*	Add helper functions to execute fuzzing multiple times	Yann Herklotz	2019-04-19	1	-9/+24
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*	Fix compiling on CI	Yann Herklotz	2019-04-19	1	-0/+3
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*	Fix some suggestions in Result.hs	Yann Herklotz	2019-04-19	1	-5/+2
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*	Equivalence test now running	Yann Herklotz	2019-04-19	1	-2/+1
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*	Extend ResultT and Result with more instances	Yann Herklotz	2019-04-19	2	-9/+46
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*	Add output information to Type	Yann Herklotz	2019-04-18	7	-80/+95
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*	Add output path to each simulator	Yann Herklotz	2019-04-18	6	-50/+121
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*	Use new fuzzing technique instead of the old function	Yann Herklotz	2019-04-17	4	-12/+29
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*	Reduce the wire size as Quartus was crashing	Yann Herklotz	2019-04-17	1	-1/+9
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*	Add new Fuzzing technique, that checks simulators against each other	Yann Herklotz	2019-04-17	1	-11/+97
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*	Add Show instances to simulators	Yann Herklotz	2019-04-17	5	-8/+25
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*	Fix tests and remove Parser tests for now	Yann Herklotz	2019-04-17	1	-5/+5
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*	Fix other type errors and replace with Result type	Yann Herklotz	2019-04-17	3	-35/+49
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*	Update simulator with Result type	Yann Herklotz	2019-04-17	5	-61/+111
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*	Add Fuzzer and implement it with the result type	Yann Herklotz	2019-04-17	1	-35/+26
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*	Move Reduce file	Yann Herklotz	2019-04-17	1	-2/+2
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*	Add Result type	Yann Herklotz	2019-04-17	1	-0/+101
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*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	12	-35/+39
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*	Format with brittany and add right modules	Yann Herklotz	2019-04-15	4	-18/+19
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*	Remove non existant exports	Yann Herklotz	2019-04-15	1	-6/+1
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*	Fix warnings	Yann Herklotz	2019-04-15	1	-9/+14
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*	Rename Synthesisor -> Synthesiser	Yann Herklotz	2019-04-15	5	-13/+13
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*	Replace Env by Fuzz	Yann Herklotz	2019-04-15	2	-58/+113
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*	Some changes to recursion schemes	Yann Herklotz	2019-04-14	1	-18/+4
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*	Remove blocking assignment from Generation	Yann Herklotz	2019-04-14	1	-1/+1
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*	Change port declarations in Reduce	Yann Herklotz	2019-04-14	1	-4/+4
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*	Print out local time	Yann Herklotz	2019-04-14	1	-2/+5
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*	Add bit vector to Icarus simulation	Yann Herklotz	2019-04-14	1	-1/+6
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*	Add Bit vector instead of using numbers	Yann Herklotz	2019-04-14	6	-184/+142
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*	Changes to general types	Yann Herklotz	2019-04-14	4	-99/+90
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*	Add Eval module to evaluate expressions	Yann Herklotz	2019-04-14	1	-0/+103
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*	Add BitVec type to model Verilog bit vectors	Yann Herklotz	2019-04-14	1	-0/+115
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*	Add Quartus implementation	Yann Herklotz	2019-04-14	1	-0/+52
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*	Merge branch 'docs'	Yann Herklotz	2019-04-13	2	-0/+12
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\| *	Add partial documentation	Yann Herklotz	2019-04-07	2	-0/+12
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* \|	Fix tests passing	Yann Herklotz	2019-04-13	2	-2/+2
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* \|	Add recursion schemes implementation	Yann Herklotz	2019-04-13	1	-0/+84
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* \|	Remove Arbitrary model	Yann Herklotz	2019-04-12	1	-226/+0
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* \|	Add for loop to design	Yann Herklotz	2019-04-12	4	-46/+135
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