| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add seeds for reproducible runs | Yann Herklotz | 2019-05-05 | 4 | -44/+83 |
| * | Add more reduction to tests | Yann Herklotz | 2019-04-29 | 1 | -2/+10 |
| * | Add random bit selection for wires | Yann Herklotz | 2019-04-26 | 6 | -44/+89 |
| * | Add time and date by default | Yann Herklotz | 2019-04-24 | 1 | -3/+17 |
| * | Add documentation to Config.hs | Yann Herklotz | 2019-04-23 | 1 | -16/+128 |
| * | Fix some errors in the templates | Yann Herklotz | 2019-04-23 | 1 | -0/+1 |
| * | Fix XST Synthesis | Yann Herklotz | 2019-04-23 | 1 | -1/+1 |
| * | Add simulator support to the config file | Yann Herklotz | 2019-04-23 | 2 | -179/+101 |
| * | Formatting files and add result type to front end | Yann Herklotz | 2019-04-23 | 5 | -6/+14 |
| * | Fix code generation for always blocks with or | Yann Herklotz | 2019-04-23 | 1 | -3/+3 |
| * | Fine tune the generation | Yann Herklotz | 2019-04-23 | 1 | -15/+13 |
| * | Add Report type | Yann Herklotz | 2019-04-23 | 1 | -0/+169 |
| * | Add event list generation for always blocks | Yann Herklotz | 2019-04-23 | 3 | -73/+4 |
| * | Add support for more event lists | Yann Herklotz | 2019-04-21 | 4 | -11/+74 |
| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -0/+1 |
| * | Add helper functions to execute fuzzing multiple times | Yann Herklotz | 2019-04-19 | 1 | -9/+24 |
| * | Fix compiling on CI | Yann Herklotz | 2019-04-19 | 1 | -0/+3 |
| * | Fix some suggestions in Result.hs | Yann Herklotz | 2019-04-19 | 1 | -5/+2 |
| * | Equivalence test now running | Yann Herklotz | 2019-04-19 | 1 | -2/+1 |
| * | Extend ResultT and Result with more instances | Yann Herklotz | 2019-04-19 | 2 | -9/+46 |
| * | Add output information to Type | Yann Herklotz | 2019-04-18 | 7 | -80/+95 |
| * | Add output path to each simulator | Yann Herklotz | 2019-04-18 | 6 | -50/+121 |
| * | Use new fuzzing technique instead of the old function | Yann Herklotz | 2019-04-17 | 4 | -12/+29 |
| * | Reduce the wire size as Quartus was crashing | Yann Herklotz | 2019-04-17 | 1 | -1/+9 |
| * | Add new Fuzzing technique, that checks simulators against each other | Yann Herklotz | 2019-04-17 | 1 | -11/+97 |
| * | Add Show instances to simulators | Yann Herklotz | 2019-04-17 | 5 | -8/+25 |
| * | Fix tests and remove Parser tests for now | Yann Herklotz | 2019-04-17 | 1 | -5/+5 |
| * | Fix other type errors and replace with Result type | Yann Herklotz | 2019-04-17 | 3 | -35/+49 |
| * | Update simulator with Result type | Yann Herklotz | 2019-04-17 | 5 | -61/+111 |
| * | Add Fuzzer and implement it with the result type | Yann Herklotz | 2019-04-17 | 1 | -35/+26 |
| * | Move Reduce file | Yann Herklotz | 2019-04-17 | 1 | -2/+2 |
| * | Add Result type | Yann Herklotz | 2019-04-17 | 1 | -0/+101 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 12 | -35/+39 |
| * | Format with brittany and add right modules | Yann Herklotz | 2019-04-15 | 4 | -18/+19 |
| * | Remove non existant exports | Yann Herklotz | 2019-04-15 | 1 | -6/+1 |
| * | Fix warnings | Yann Herklotz | 2019-04-15 | 1 | -9/+14 |
| * | Rename Synthesisor -> Synthesiser | Yann Herklotz | 2019-04-15 | 5 | -13/+13 |
| * | Replace Env by Fuzz | Yann Herklotz | 2019-04-15 | 2 | -58/+113 |
| * | Some changes to recursion schemes | Yann Herklotz | 2019-04-14 | 1 | -18/+4 |
| * | Remove blocking assignment from Generation | Yann Herklotz | 2019-04-14 | 1 | -1/+1 |
| * | Change port declarations in Reduce | Yann Herklotz | 2019-04-14 | 1 | -4/+4 |
| * | Print out local time | Yann Herklotz | 2019-04-14 | 1 | -2/+5 |
| * | Add bit vector to Icarus simulation | Yann Herklotz | 2019-04-14 | 1 | -1/+6 |
| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 6 | -184/+142 |
| * | Changes to general types | Yann Herklotz | 2019-04-14 | 4 | -99/+90 |
| * | Add Eval module to evaluate expressions | Yann Herklotz | 2019-04-14 | 1 | -0/+103 |
| * | Add BitVec type to model Verilog bit vectors | Yann Herklotz | 2019-04-14 | 1 | -0/+115 |
| * | Add Quartus implementation | Yann Herklotz | 2019-04-14 | 1 | -0/+52 |
| * | Merge branch 'docs' | Yann Herklotz | 2019-04-13 | 2 | -0/+12 |
| |\ | |||||
| | * | Add partial documentation | Yann Herklotz | 2019-04-07 | 2 | -0/+12 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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