Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Format fixes | Yann Herklotz | 2018-12-27 | 1 | -20/+20 |
* | Small style change | Yann Herklotz | 2018-12-27 | 1 | -1/+1 |
* | Improve expression and statement generation | Yann Herklotz | 2018-12-27 | 1 | -20/+96 |
* | Add documentation to main module | Yann Herklotz | 2018-12-25 | 1 | -0/+13 |
* | Add code generation for new types | Yann Herklotz | 2018-12-25 | 1 | -20/+130 |
* | Type fixes | Yann Herklotz | 2018-12-25 | 1 | -7/+8 |
* | Rename Node to Int | Yann Herklotz | 2018-12-25 | 1 | -1/+1 |
* | [Close #10, Fix #12] Add Mutations for wires | Yann Herklotz | 2018-12-25 | 1 | -7/+13 |
* | Add more types | Yann Herklotz | 2018-12-25 | 1 | -41/+181 |
* | Add Helpers.hs | Yann Herklotz | 2018-12-25 | 1 | -0/+75 |
* | Fix nesting, generation broken for nested groups | Yann Herklotz | 2018-12-23 | 1 | -3/+17 |
* | Add nesting to the SourceText | Yann Herklotz | 2018-12-23 | 1 | -1/+16 |
* | [Fix #11] Implement the traversal | Yann Herklotz | 2018-12-23 | 1 | -18/+32 |
* | Start implementing the nesting functionality | Yann Herklotz | 2018-12-23 | 1 | -2/+23 |
* | Derive `Eq` for the Verilog AST. | Yann Herklotz | 2018-12-22 | 2 | -13/+14 |
* | Add unimplemented nestId function | Yann Herklotz | 2018-12-22 | 1 | -0/+4 |
* | Add Mutate module to VeriFuzz | Yann Herklotz | 2018-12-22 | 2 | -0/+17 |
* | Format ASTGen | Yann Herklotz | 2018-12-22 | 1 | -6/+3 |
* | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 4 | -19/+33 |
* | Add shared code to code generation | Yann Herklotz | 2018-12-22 | 1 | -0/+34 |
* | Add more functions to the code generation | Yann Herklotz | 2018-12-22 | 2 | -25/+21 |
* | Add more AST generation | Yann Herklotz | 2018-12-20 | 1 | -1/+19 |
* | Fix documentation | Yann Herklotz | 2018-12-15 | 5 | -15/+117 |
* | Add new imports | Yann Herklotz | 2018-12-15 | 1 | -3/+5 |
* | Add AST generation | Yann Herklotz | 2018-12-15 | 1 | -0/+47 |
* | Rename types to circuit | Yann Herklotz | 2018-12-15 | 1 | -1/+15 |
* | [Fix #1] Fix the negative number generation | Yann Herklotz | 2018-12-04 | 2 | -2/+5 |
* | [Fix #8] Add Circuit newtype | Yann Herklotz | 2018-12-02 | 1 | -0/+3 |
* | Fix typo | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
* | Add newline after module declaration | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
* | Fix the code generation | Yann Herklotz | 2018-12-01 | 1 | -1/+13 |
* | Add all arbitrary instances and fix identifier | Yann Herklotz | 2018-12-01 | 1 | -15/+65 |
* | Add more code to the shared code | Yann Herklotz | 2018-12-01 | 2 | -15/+15 |
* | Add modport helper function | Yann Herklotz | 2018-12-01 | 1 | -0/+3 |
* | Add more code generation for expressions | Yann Herklotz | 2018-12-01 | 1 | -0/+40 |
* | Add missing modules to main library | Yann Herklotz | 2018-12-01 | 1 | -0/+2 |
* | Add internal shared module | Yann Herklotz | 2018-12-01 | 1 | -0/+4 |
* | Move generation to new location | Yann Herklotz | 2018-12-01 | 2 | -59/+79 |
* | [lint] Remove unnecessary '$' | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
* | Fix data types and apply more hlint suggestions | Yann Herklotz | 2018-12-01 | 1 | -8/+6 |
* | Add helper methods | Yann Herklotz | 2018-12-01 | 1 | -6/+15 |
* | Add assignment to ModuleItem | Yann Herklotz | 2018-11-30 | 1 | -3/+2 |
* | Add more types | Yann Herklotz | 2018-11-30 | 1 | -12/+25 |
* | Fix type issue in main | Yann Herklotz | 2018-11-30 | 1 | -5/+10 |
* | Restructure and add tests | Yann Herklotz | 2018-11-30 | 1 | -19/+0 |
* | Add lens library and extend types for AST | Yann Herklotz | 2018-11-30 | 1 | -5/+65 |
* | Add AST to the exported modules | Yann Herklotz | 2018-11-30 | 1 | -0/+3 |
* | Add some simplifications (map -> fmap) | Yann Herklotz | 2018-11-29 | 1 | -5/+6 |
* | Add Verilog AST | Yann Herklotz | 2018-11-29 | 1 | -0/+13 |
* | Improve generation | Yann Herklotz | 2018-11-16 | 1 | -15/+15 |