verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Run through brittany	Yann Herklotz	2019-04-01	6	-184/+199
*	Fix warnings in code	Yann Herklotz	2019-03-31	2	-25/+7
*	Fix some of the tests	Yann Herklotz	2019-03-31	1	-1/+2
*	Rewrite the parser with real lexer	Yann Herklotz	2019-03-31	8	-579/+970
*	Add documentation	Yann Herklotz	2019-03-30	1	-10/+28
*	Add if statement type	Yann Herklotz	2019-03-30	1	-0/+4
*	Useful renames and add if statement generation	Yann Herklotz	2019-03-30	1	-141/+143
*	Add some documentation	Yann Herklotz	2019-03-30	1	-9/+14
*	Change license name	Yann Herklotz	2019-03-30	22	-22/+22
*	Add more options to main app	Yann Herklotz Grave	2019-03-07	1	-8/+8
*	Fix build	Yann Herklotz Grave	2019-03-07	1	-11/+0
*	Add proper register generation	Yann Herklotz Grave	2019-03-07	2	-15/+17
*	Fix build errors and simplify names	Yann Herklotz Grave	2019-03-06	1	-33/+42
*	Add always blocks to the main generation	Yann Herklotz Grave	2019-03-06	1	-7/+44
*	Add more probabilities to config	Yann Herklotz Grave	2019-03-06	2	-24/+28
*	Rename Stmnt to Statement	Yann Herklotz Grave	2019-03-06	3	-37/+37
*	Hlint suggestions	Yann Herklotz Grave	2019-03-06	1	-4/+4
*	Fix positive arbitrary generation	Yann Herklotz Grave	2019-03-06	1	-1/+1
*	Add more configuration options	Yann Herklotz Grave	2019-03-06	1	-6/+54
*	Run formatting on Config.hs	Yann Herklotz Grave	2019-03-04	1	-6/+12
*	Create procedural generation for Verilog	Yann Herklotz Grave	2019-03-04	1	-12/+3
*	Add toml configuration support for probabilities	Yann Herklotz Grave	2019-03-04	2	-0/+59
*	Fix all the warnings and fix building	Yann Herklotz Grave	2019-03-03	1	-10/+15
*	Add transformers and procedural generation	Yann Herklotz Grave	2019-03-03	4	-24/+100
*	Add .gitAttributes	Yann Herklotz Grave	2019-03-03	1	-1/+1
*	Add applicative instance and Expr reduction	Yann Herklotz Grave	2019-03-02	1	-20/+48
*	Some formatting	Yann Herklotz Grave	2019-03-01	1	-4/+4
*	Add better reduction with custom type	Yann Herklotz Grave	2019-03-01	1	-48/+73
*	Add lens to access main module in SourceInfo	Yann Herklotz Grave	2019-03-01	3	-7/+23
*	Lint fix	Yann Herklotz Grave	2019-03-01	1	-1/+1
*	[Fix #35] Add reducer that tries and reduce Verilog given a run	Yann Herklotz Grave	2019-03-01	1	-24/+94
*	[Fix #38] Fix parser to correctly identify input and output ports	Yann Herklotz Grave	2019-03-01	1	-2/+13
*	Add general function to mutations	Yann Herklotz Grave	2019-03-01	1	-1/+7
*	[Fix #37] Fix types in the simulator with more general functions	Yann Herklotz Grave	2019-03-01	3	-55/+63
*	Add missing modules to Internal module	Yann Herklotz Grave	2019-03-01	1	-1/+3
*	Add Simulation and Synthesis environments	Yann Herklotz Grave	2019-03-01	1	-12/+31
*	Fix indentation	Yann Herklotz Grave	2019-03-01	1	-19/+22
*	Fix warnings in ASTGen and make it more general	Yann Herklotz Grave	2019-03-01	1	-11/+9
*	[Fix #34, Fix #36] Add Ord instance to AST	Yann Herklotz Grave	2019-03-01	1	-49/+60
*	Fixing exports and imports in main library	Yann Herklotz Grave	2019-03-01	1	-13/+29
*	Applying stylish-haskell	Yann Herklotz Grave	2019-03-01	2	-15/+13
*	Moving general simulator options into Internal	Yann Herklotz Grave	2019-03-01	3	-150/+173
*	Add documentation to main VeriFuzz module	Yann Herklotz Grave	2019-02-26	1	-0/+11
*	Add Ord to AST and fix reduction function	Yann Herklotz Grave	2019-02-26	2	-24/+26
*	Add recursive reduce call	Yann Herklotz Grave	2019-02-25	2	-6/+35
*	Reformat using brittany	Yann Herklotz Grave	2019-02-25	14	-88/+187
*	Indent by 4	Yann Herklotz Grave	2019-02-17	17	-694/+699
*	Brittany formatting	Yann Herklotz Grave	2019-02-17	16	-231/+347
*	Add Parser to Main.hs	Yann Herklotz Grave	2019-02-17	1	-1/+5
*	Fix example in documentation	Yann Herklotz Grave	2019-02-16	1	-1/+1