verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add option to drop reg and wire from output	Yann Herklotz	2020-04-09	3	-18/+74
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*	Remove shakespeare dependency	Yann Herklotz	2020-04-07	3	-102/+103
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*	Remove statistic dependency	Yann Herklotz	2020-04-07	1	-3/+9
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*	Remove DRBG dependency	Yann Herklotz	2020-04-07	3	-31/+34
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*	Add annotations and make it compile again	Yann Herklotz	2020-04-07	11	-31/+41
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*	WIP changes to the AST types	Yann Herklotz	2020-03-16	21	-212/+210
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*	Changes to AST to support annotations	Yann Herklotz	2020-03-04	1	-289/+305
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*	Fix spacing in the generated Verilog	Yann Herklotz	2020-03-03	1	-16/+20
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*	Add case statement to the AST	Yann Herklotz	2020-03-03	2	-1/+41
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*	Update license notices	Yann Herklotz	2020-01-06	35	-35/+35
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*	Update license to dual license GPLv3	Yann Herklotz	2020-01-06	35	-35/+35
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*	Add correct cleaning function back	Yann Herklotz	2019-12-26	1	-1/+1
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*	Add configuration for default Yosys location	Yann Herklotz	2019-12-26	3	-7/+28
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*	Update documentation	Yann Herklotz	2019-12-26	1	-26/+49
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*	Add reduction stage back	Yann Herklotz	2019-12-26	1	-0/+1
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*	Add quartuslight	Yann Herklotz	2019-12-10	1	-2/+2
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*	Do not run counter example if no rerunner is specified	Yann Herklotz	2019-12-03	7	-26/+40
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*	Set aigsmt to none	Yann Herklotz	2019-12-03	1	-1/+1
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*	More minimisation	Yann Herklotz	2019-12-03	1	-3/+9
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*	Add different identifier for forloops	Yann Herklotz	2019-11-24	1	-15/+17
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*	Add ModConnNamed in testbench	Yann Herklotz	2019-11-24	1	-1/+1
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*	Add extension to simulation reduction	Yann Herklotz	2019-11-24	1	-1/+1
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*	Fix more changes to for loops	Yann Herklotz	2019-11-24	1	-1/+1
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*	Do not mutate the expression in the for loop	Yann Herklotz	2019-11-24	1	-1/+1
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*	Fix build	Yann Herklotz	2019-11-24	1	-1/+1
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*	Add output of v file during reduction	Yann Herklotz	2019-11-24	2	-35/+20
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*	Show the result as it is run	Yann Herklotz	2019-11-24	1	-4/+4
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*	Add cross-check between netlists	Yann Herklotz	2019-11-24	3	-11/+16
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*	Fix counter-example simulation run	Yann Herklotz	2019-11-24	1	-1/+1
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*	Support proper Quartus Pro version	Yann Herklotz	2019-11-14	5	-40/+166
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*	Add delay to finish	Yann Herklotz	2019-11-14	1	-1/+1
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*	Add z3 as default equivalence check with ABC	Yann Herklotz	2019-11-14	1	-0/+1
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*	Add reduction for simulation failures	Yann Herklotz	2019-11-12	6	-70/+174
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*	Use text to store counter-example	Yann Herklotz	2019-11-12	1	-15/+15
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*	Add counter example parsing	Yann Herklotz	2019-11-10	7	-47/+164
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*	Add reduction pass to remove constants from concat	Yann Herklotz	2019-11-05	4	-7/+57
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*	Add support for Quartus using projects	Yann Herklotz	2019-11-04	2	-17/+45
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*	Add parsing of existing rtl when starting fuzz run	Yann Herklotz	2019-10-31	2	-10/+31
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*	Add data-file installation path	Yann Herklotz	2019-10-29	6	-38/+56
\| \| \| \| \|	This removes the need to recursively copy the data directory which will also save on space.
*	Run simulation on all tools passing synthesis	Yann Herklotz	2019-10-28	1	-20/+27
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*	Add --no-reduction	Yann Herklotz	2019-10-28	2	-23/+20
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*	Add mtl dependency to enable easier use of transformers	Yann Herklotz	2019-10-27	2	-142/+172
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*	Add OptParser to separate option parsing	Yann Herklotz	2019-10-27	2	-245/+270
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*	Add comment to code generation	Yann Herklotz	2019-10-25	1	-1/+1
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*	Add the literal list to the mod instantiation	Yann Herklotz	2019-10-25	1	-2/+3
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*	Fix subtle issue with module generation	Yann Herklotz	2019-10-25	1	-0/+1
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*	Change location of the html reports	Yann Herklotz	2019-10-18	2	-4/+6
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*	Add -k functionality	Yann Herklotz	2019-10-18	3	-9/+31
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*	Rename Sim to Tool	Yann Herklotz	2019-10-18	14	-68/+63
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*	[Fix #63] Make build pass again	Yann Herklotz	2019-10-06	2	-57/+54
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